diff options
Diffstat (limited to 'tcl')
42 files changed, 69 insertions, 69 deletions
diff --git a/tcl/board/at91eb40a.cfg b/tcl/board/at91eb40a.cfg index 40f2e123..14f21a1a 100644 --- a/tcl/board/at91eb40a.cfg +++ b/tcl/board/at91eb40a.cfg @@ -65,4 +65,4 @@ $_TARGETNAME configure -event reset-init { } # This target is pretty snappy... -jtag_khz 16000 +adapter_khz 16000 diff --git a/tcl/board/at91rm9200-dk.cfg b/tcl/board/at91rm9200-dk.cfg index 9a6f89e6..476f5a80 100644 --- a/tcl/board/at91rm9200-dk.cfg +++ b/tcl/board/at91rm9200-dk.cfg @@ -15,7 +15,7 @@ flash_bank cfi 0x10000000 0x00200000 2 2 0 proc at91rm9200_dk_init { } { # Try to run at 1khz... Yea, that slow! # Chip is really running @ 32khz - jtag_khz 8 + adapter_khz 8 mww 0xfffffc64 0xffffffff ## disable all clocks but system clock @@ -41,7 +41,7 @@ proc at91rm9200_dk_init { } { #======================================== # CPU now runs at 180mhz # SYS runs at 60mhz. - jtag_khz 40000 + adapter_khz 40000 #======================================== diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg index fb6068cc..f24f1a13 100644 --- a/tcl/board/at91sam9g20-ek.cfg +++ b/tcl/board/at91sam9g20-ek.cfg @@ -77,7 +77,7 @@ proc at91sam9g20_init { } { # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly. - jtag_khz 2 # Slow-speed oscillator enabled at reset, so run jtag speed slow. + adapter_khz 2 # Slow-speed oscillator enabled at reset, so run jtag speed slow. halt # Make sure processor is halted, or error will result in following steps. mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset. mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog. @@ -112,7 +112,7 @@ proc at91sam9g20_init { } { # Switch over to adaptive clocking. - jtag_khz 0 + adapter_khz 0 # Enable faster DCC downloads. diff --git a/tcl/board/csb337.cfg b/tcl/board/csb337.cfg index b7bce489..5e225f5f 100644 --- a/tcl/board/csb337.cfg +++ b/tcl/board/csb337.cfg @@ -19,7 +19,7 @@ if { [info exists ETM_DRIVER] } { proc csb337_clk_init { } { # CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock - jtag_khz 8 + adapter_khz 8 # CKGR_MOR: start main oscillator (3.6864 MHz) mww 0xfffffc20 0xff01 @@ -37,7 +37,7 @@ proc csb337_clk_init { } { sleep 20 # CPU is in Normal Mode ... allows faster JTAG clock speed - jtag_khz 40000 + adapter_khz 40000 } proc csb337_nor_init { } { diff --git a/tcl/board/dm365evm.cfg b/tcl/board/dm365evm.cfg index f8ec4e04..8f268c45 100644 --- a/tcl/board/dm365evm.cfg +++ b/tcl/board/dm365evm.cfg @@ -103,7 +103,7 @@ proc dm365evm_init {} { echo "Initialize DM365 EVM board" # CLKIN = 24 MHz ... can't talk quickly to ARM yet - jtag_khz 1500 + adapter_khz 1500 # FIXME -- PLL init diff --git a/tcl/board/ek-lm3s1968.cfg b/tcl/board/ek-lm3s1968.cfg index bf4b0972..6ce7f7fa 100644 --- a/tcl/board/ek-lm3s1968.cfg +++ b/tcl/board/ek-lm3s1968.cfg @@ -4,7 +4,7 @@ # http://www.luminarymicro.com/products/lm3s1968_evaluation_kits.html # NOTE: to use J-Link instead of the on-board interface, -# you may also need to reduce jtag_khz to be about 1200. +# you may also need to reduce adapter_khz to be about 1200. # source [find interface/jlink.cfg] # include the FT2232 interface config for on-board JTAG interface @@ -14,7 +14,7 @@ source [find interface/luminary.cfg] source [find target/lm3s1968.cfg] # jtag speed -jtag_khz 3000 +adapter_khz 3000 jtag_nsrst_delay 100 diff --git a/tcl/board/ek-lm3s811.cfg b/tcl/board/ek-lm3s811.cfg index 5825c23d..078cae1f 100644 --- a/tcl/board/ek-lm3s811.cfg +++ b/tcl/board/ek-lm3s811.cfg @@ -10,7 +10,7 @@ source [find interface/luminary.cfg] source [find target/lm3s811.cfg] # jtag speed -jtag_khz 500 +adapter_khz 500 jtag_nsrst_delay 100 diff --git a/tcl/board/ek-lm3s9b9x.cfg b/tcl/board/ek-lm3s9b9x.cfg index 407ecc80..b8be88b8 100644 --- a/tcl/board/ek-lm3s9b9x.cfg +++ b/tcl/board/ek-lm3s9b9x.cfg @@ -9,7 +9,7 @@ source [find interface/luminary-icdi.cfg] source [find target/lm3s9b9x.cfg] # jtag speed -jtag_khz 500 +adapter_khz 500 jtag_nsrst_delay 100 diff --git a/tcl/board/ethernut3.cfg b/tcl/board/ethernut3.cfg index f22e6887..359cb0bf 100644 --- a/tcl/board/ethernut3.cfg +++ b/tcl/board/ethernut3.cfg @@ -26,7 +26,7 @@ jtag_ntrst_delay 300 arm7_9 fast_memory_access enable arm7_9 dcc_downloads enable -jtag_khz 16000 +adapter_khz 16000 # Target events diff --git a/tcl/board/hitex_lpc2929.cfg b/tcl/board/hitex_lpc2929.cfg index 7d06f745..35cc7d0b 100644 --- a/tcl/board/hitex_lpc2929.cfg +++ b/tcl/board/hitex_lpc2929.cfg @@ -7,7 +7,7 @@ jtag_ntrst_delay 1 # Maximum of 1/8 of clock frequency (XTAL = 16 MHz). # Adaptive clocking through RTCK is not supported. -jtag_khz 2000 +adapter_khz 2000 # Target device: LPC29xx with ETB # The following variables are used by the LPC2900 script: @@ -24,7 +24,7 @@ $_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size 0x10000 -work- # Event handlers $_TARGETNAME configure -event reset-start { # Back to the slow JTAG clock - jtag_khz 2000 + adapter_khz 2000 } # External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB) @@ -46,7 +46,7 @@ $_TARGETNAME configure -event reset-init { mww 0xFFFF8070 0x02000000 # SYS_CLK_CONF: PLL # Increase JTAG speed - jtag_khz 6000 + adapter_khz 6000 # Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7) mww 0xE0001138 0x0000001F # P1.14 = D0 diff --git a/tcl/board/hitex_str9-comstick.cfg b/tcl/board/hitex_str9-comstick.cfg index af7527a1..ade24f62 100644 --- a/tcl/board/hitex_str9-comstick.cfg +++ b/tcl/board/hitex_str9-comstick.cfg @@ -5,7 +5,7 @@ source [find interface/hitex_str9-comstick.cfg] # set jtag speed -jtag_khz 3000 +adapter_khz 3000 jtag_nsrst_delay 100 jtag_ntrst_delay 100 diff --git a/tcl/board/imx27lnst.cfg b/tcl/board/imx27lnst.cfg index ae141d41..e0ed0579 100644 --- a/tcl/board/imx27lnst.cfg +++ b/tcl/board/imx27lnst.cfg @@ -8,7 +8,7 @@ proc imx27lnst_init { } { # This setup puts RAM at 0xA0000000 # reset the board correctly - jtag_khz 500 + adapter_khz 500 reset run reset halt diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg index 47bebc43..b053c225 100644 --- a/tcl/board/mini2440.cfg +++ b/tcl/board/mini2440.cfg @@ -121,7 +121,7 @@ reset_config trst_and_srst # IMPORTANT! See README at top of this file. #------------------------------------------------------------------------- - jtag_khz 12000 + adapter_khz 12000 jtag interface #------------------------------------------------------------------------- diff --git a/tcl/board/phytec_lpc3250.cfg b/tcl/board/phytec_lpc3250.cfg index 78cb90de..51622ef1 100644 --- a/tcl/board/phytec_lpc3250.cfg +++ b/tcl/board/phytec_lpc3250.cfg @@ -2,7 +2,7 @@ source [find target/lpc3250.cfg] jtag_nsrst_delay 200 jtag_ntrst_delay 1 -jtag_khz 200 +adapter_khz 200 reset_config trst_and_srst separate arm7_9 dcc_downloads enable @@ -11,11 +11,11 @@ $_TARGETNAME configure -event gdb-attach { reset init } $_TARGETNAME configure -event reset-start { arm7_9 fast_memory_access disable - jtag_khz 200 + adapter_khz 200 } $_TARGETNAME configure -event reset-end { - jtag_khz 6000 + adapter_khz 6000 arm7_9 fast_memory_access enable } diff --git a/tcl/board/telo.cfg b/tcl/board/telo.cfg index 0cbdb816..cb4bc2a3 100644 --- a/tcl/board/telo.cfg +++ b/tcl/board/telo.cfg @@ -26,11 +26,11 @@ reset_config trst_and_srst separate # issue telnet: reset init # issue gdb: monitor reset init $_TARGETNAME configure -event reset-init { - jtag_khz 100 + adapter_khz 100 # this will setup Telo board setupTelo #turn up the JTAG speed - jtag_khz 3000 + adapter_khz 3000 puts "JTAG speek now 3MHz" puts "type helpC100 to get help on C100" } diff --git a/tcl/board/topas910.cfg b/tcl/board/topas910.cfg index ae72c4b7..303fc778 100644 --- a/tcl/board/topas910.cfg +++ b/tcl/board/topas910.cfg @@ -99,7 +99,7 @@ proc topas910_init { } { mww 0xf4300004 0x00000000 sleep 10 -# jtag_khz NNNN +# adapter_khz NNNN # remap off in case of IROM boot mww 0xf0000004 0x00000001 diff --git a/tcl/board/topasa900.cfg b/tcl/board/topasa900.cfg index 5984f81f..aa3f77f2 100644 --- a/tcl/board/topasa900.cfg +++ b/tcl/board/topasa900.cfg @@ -105,7 +105,7 @@ proc topasa900_init { } { mww 0xf4300004 0x00000000 sleep 10 -# jtag_khz NNNN +# adapter_khz NNNN # remap off in case of IROM boot mww 0xf0000004 0x00000001 diff --git a/tcl/board/zy1000.cfg b/tcl/board/zy1000.cfg index 8278fa46..17594c2f 100644 --- a/tcl/board/zy1000.cfg +++ b/tcl/board/zy1000.cfg @@ -66,7 +66,7 @@ $_TARGETNAME configure -event reset-init { # other things than flash programming. $_TARGETNAME configure -work-area-phys 0x00020000 -work-area-size 0x20000 -work-area-backup 0 -jtag_khz 16000 +adapter_khz 16000 proc production_info {} { diff --git a/tcl/interface/altera-usb-blaster.cfg b/tcl/interface/altera-usb-blaster.cfg index ae214652..9f542d0a 100644 --- a/tcl/interface/altera-usb-blaster.cfg +++ b/tcl/interface/altera-usb-blaster.cfg @@ -8,4 +8,4 @@ interface usb_blaster # These are already the defaults. # usb_blaster_vid_pid 0x09FB 0x6001 # usb_blaster_device_desc "USB-Blaster" -jtag_khz 3000 +adapter_khz 3000 diff --git a/tcl/interface/oocdlink.cfg b/tcl/interface/oocdlink.cfg index 9022afd2..4e962f52 100644 --- a/tcl/interface/oocdlink.cfg +++ b/tcl/interface/oocdlink.cfg @@ -8,5 +8,5 @@ interface ft2232 ft2232_device_desc "OOCDLink" ft2232_layout oocdlink ft2232_vid_pid 0x0403 0xbaf8 -jtag_khz 5 +adapter_khz 5 diff --git a/tcl/interface/openrd.cfg b/tcl/interface/openrd.cfg index b01205be..322b508b 100644 --- a/tcl/interface/openrd.cfg +++ b/tcl/interface/openrd.cfg @@ -8,5 +8,5 @@ interface ft2232 ft2232_layout sheevaplug ft2232_vid_pid 0x0403 0x9e90 ft2232_device_desc "OpenRD JTAGKey FT2232D B" -jtag_khz 3000 +adapter_khz 3000 diff --git a/tcl/interface/sheevaplug.cfg b/tcl/interface/sheevaplug.cfg index 556f44d5..d46d71e2 100644 --- a/tcl/interface/sheevaplug.cfg +++ b/tcl/interface/sheevaplug.cfg @@ -8,5 +8,5 @@ interface ft2232 ft2232_layout sheevaplug ft2232_vid_pid 0x9e88 0x9e8f ft2232_device_desc "SheevaPlug JTAGKey FT2232D B" -jtag_khz 2000 +adapter_khz 2000 diff --git a/tcl/interface/usb-jtag.cfg b/tcl/interface/usb-jtag.cfg index b81028d6..a3db11e3 100644 --- a/tcl/interface/usb-jtag.cfg +++ b/tcl/interface/usb-jtag.cfg @@ -7,5 +7,5 @@ interface usb_blaster usb_blaster_vid_pid 0x16C0 0x06AD usb_blaster_device_desc "USB-JTAG-IF" -jtag_khz 3000 +adapter_khz 3000 diff --git a/tcl/interface/vsllink.cfg b/tcl/interface/vsllink.cfg index 7c9de7fe..07a5a068 100644 --- a/tcl/interface/vsllink.cfg +++ b/tcl/interface/vsllink.cfg @@ -19,7 +19,7 @@ vsllink_usb_bulkout 0x03 vsllink_usb_interface 1 # vsllink mode, dma or normal -# for low jtag_khz, use normal -# for high jtag_khz, use dma +# for low adapter_khz, use normal +# for high adapter_khz, use dma #vsllink_mode dma vsllink_mode normal diff --git a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg index 690406bb..03595404 100644 --- a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg +++ b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg @@ -1,7 +1,7 @@ -jtag_khz 4 +adapter_khz 4 ###################################### @@ -62,7 +62,7 @@ flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME proc at91sam_init { } { # at reset chip runs at 32khz - jtag_khz 8 + adapter_khz 8 halt mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog @@ -79,7 +79,7 @@ proc at91sam_init { } { sleep 10 # wait 10 ms # Now run at anything fast... ie: 10mhz! - jtag_khz 10000 # Increase JTAG Speed to 6 MHz + adapter_khz 10000 # Increase JTAG Speed to 6 MHz arm7_9 dcc_downloads enable # Enable faster DCC downloads mww 0xffffec00 0x0a0a0a0a # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit diff --git a/tcl/target/c100.cfg b/tcl/target/c100.cfg index b175f23f..23eca0c7 100644 --- a/tcl/target/c100.cfg +++ b/tcl/target/c100.cfg @@ -3,7 +3,7 @@ # this script only configures one core (that is used to run Linux) # assume no PLL lock, start slowly -jtag_khz 100 +adapter_khz 100 if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl index 96588713..1fd58b65 100644 --- a/tcl/target/c100helper.tcl +++ b/tcl/target/c100helper.tcl @@ -504,7 +504,7 @@ proc reboot {} { mww $TIMER_WDT_HIGH_BOUND 0xffffff mww $TIMER_WDT_CURRENT_COUNT 0x0 puts "JTAG speed lowered to 100kHz" - jtag_khz 100 + adapter_khz 100 mww $TIMER_WDT_CONTROL 0x1 # wait until the reset puts -nonewline "Wating for watchdog to trigger..." diff --git a/tcl/target/dsp56321.cfg b/tcl/target/dsp56321.cfg index 45068370..281c4ddd 100644 --- a/tcl/target/dsp56321.cfg +++ b/tcl/target/dsp56321.cfg @@ -22,7 +22,7 @@ if { [info exists CPUTAPID ] } { } #jtag speed -jtag_khz 4500 +adapter_khz 4500 #has only srst reset_config srst_only diff --git a/tcl/target/lm3s6965.cfg b/tcl/target/lm3s6965.cfg index 02d85d46..c6e623ee 100644 --- a/tcl/target/lm3s6965.cfg +++ b/tcl/target/lm3s6965.cfg @@ -13,7 +13,7 @@ if { [info exists CPUTAPID ] } { } # jtag speed -jtag_khz 500 +adapter_khz 500 jtag_nsrst_delay 100 jtag_ntrst_delay 100 diff --git a/tcl/target/lpc2124.cfg b/tcl/target/lpc2124.cfg index 9a27aece..ce55952a 100644 --- a/tcl/target/lpc2124.cfg +++ b/tcl/target/lpc2124.cfg @@ -27,7 +27,7 @@ reset_config trst_and_srst srst_pulls_trst jtag_nsrst_delay 100 jtag_ntrst_delay 100 -jtag_khz 1000 +adapter_khz 1000 #jtag scan chain jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID diff --git a/tcl/target/lpc2378.cfg b/tcl/target/lpc2378.cfg index 4e50ac5c..7eb0dabb 100644 --- a/tcl/target/lpc2378.cfg +++ b/tcl/target/lpc2378.cfg @@ -47,4 +47,4 @@ set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME lpc2000 0x0 0x0007D000 0 0 $_TARGETNAME lpc2000_v2 4000 calc_checksum # 4MHz / 6 = 666kHz, so use 500 -jtag_khz 500 +adapter_khz 500 diff --git a/tcl/target/mc13224v.cfg b/tcl/target/mc13224v.cfg index 497e376e..33351caf 100644 --- a/tcl/target/mc13224v.cfg +++ b/tcl/target/mc13224v.cfg @@ -36,7 +36,7 @@ jtag_ntrst_delay 200 # rclk hasn't been working well. This maybe the mc13224v or something else. #jtag_rclk 2000 -jtag_khz 2000 +adapter_khz 2000 ###################### # Target configuration diff --git a/tcl/target/mega128.cfg b/tcl/target/mega128.cfg index 2cf31d61..697ec45b 100644 --- a/tcl/target/mega128.cfg +++ b/tcl/target/mega128.cfg @@ -4,7 +4,7 @@ set _ENDIAN little # jtag speed -jtag_khz 4500 +adapter_khz 4500 reset_config srst_only jtag_nsrst_delay 100 @@ -27,7 +27,7 @@ flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME #to use it, script will be like: #init -#jtag_khz 4500 +#adapter_khz 4500 #reset init #verify_ircapture disable # diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg index 44efdaa4..5b745f85 100644 --- a/tcl/target/pxa255.cfg +++ b/tcl/target/pxa255.cfg @@ -28,8 +28,8 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \ # PXA255 comes out of reset using 3.6864 MHz oscillator. # Until the PLL kicks in, keep the JTAG clock slow enough # that we get no errors. -jtag_khz 300 -$_TARGETNAME configure -event "reset-start" { jtag_khz 300 } +adapter_khz 300 +$_TARGETNAME configure -event "reset-start" { adapter_khz 300 } # both TRST and SRST are *required* for debug # DCSR is often accessed with SRST active diff --git a/tcl/target/readme.txt b/tcl/target/readme.txt index 39f8d124..f028b11c 100644 --- a/tcl/target/readme.txt +++ b/tcl/target/readme.txt @@ -26,12 +26,12 @@ assumed that all write-protect mechanisms should be disabled. flash write_image [file] <parameters> verify_image [file] <parameters> -4. jtag_khz sets the maximum speed (or alternatively RCLK). If invoked +4. adapter_khz sets the maximum speed (or alternatively RCLK). If invoked multiple times only the last setting is used. interface/xxx.cfg files are always executed *before* target/xxx.cfg -files, so any jtag_khz in interface/xxx.cfg will be overridden by -target/xxx.cfg. jtag_khz in interface/xxx.cfg would then, effectively, +files, so any adapter_khz in interface/xxx.cfg will be overridden by +target/xxx.cfg. adapter_khz in interface/xxx.cfg would then, effectively, set the default JTAG speed. Note that a target/xxx.cfg file can invoke another target/yyy.cfg file, diff --git a/tcl/target/samsung_s3c2450.cfg b/tcl/target/samsung_s3c2450.cfg index 071b271a..00754260 100644 --- a/tcl/target/samsung_s3c2450.cfg +++ b/tcl/target/samsung_s3c2450.cfg @@ -7,11 +7,11 @@ # # RCLK? # -# jtag_khz 0 +# adapter_khz 0 # # Really low clock during reset? # -# jtag_khz 1 +# adapter_khz 1 if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg index 6fafac94..5f4428f5 100644 --- a/tcl/target/stellaris.cfg +++ b/tcl/target/stellaris.cfg @@ -41,8 +41,8 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000 # NOTE: this may be increased by a reset-init handler, after it # configures and enables the PLL. Or you might need to decrease # this, if you're using a slower clock. -jtag_khz 500 -$_TARGETNAME configure -event reset-start {jtag_khz 500} +adapter_khz 500 +$_TARGETNAME configure -event reset-start {adapter_khz 500} # flash configuration ... autodetects sizes, autoprobed flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME diff --git a/tcl/target/stm32.cfg b/tcl/target/stm32.cfg index 463a85cf..29c9f7ff 100644 --- a/tcl/target/stm32.cfg +++ b/tcl/target/stm32.cfg @@ -21,7 +21,7 @@ if { [info exists WORKAREASIZE] } { } # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz -jtag_khz 1000 +adapter_khz 1000 jtag_nsrst_delay 100 jtag_ntrst_delay 100 diff --git a/tcl/target/str710.cfg b/tcl/target/str710.cfg index 028c6043..4d685865 100644 --- a/tcl/target/str710.cfg +++ b/tcl/target/str710.cfg @@ -1,5 +1,5 @@ #start slow, speed up after reset -jtag_khz 10 +adapter_khz 10 if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME @@ -29,9 +29,9 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_C set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi -$_TARGETNAME configure -event reset-start { jtag_khz 10 } +$_TARGETNAME configure -event reset-start { adapter_khz 10 } $_TARGETNAME configure -event reset-init { - jtag_khz 6000 + adapter_khz 6000 # Because the hardware cannot be interrogated for the protection state # of sectors, initialize all the sectors to be unprotected. The initial diff --git a/tcl/target/str730.cfg b/tcl/target/str730.cfg index 09179531..3a84897c 100644 --- a/tcl/target/str730.cfg +++ b/tcl/target/str730.cfg @@ -1,6 +1,6 @@ #STR730 CPU -jtag_khz 3000 +adapter_khz 3000 if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME @@ -33,9 +33,9 @@ jtag_ntrst_delay 500 set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi -$_TARGETNAME configure -event reset-start { jtag_khz 10 } +$_TARGETNAME configure -event reset-start { adapter_khz 10 } $_TARGETNAME configure -event reset-init { - jtag_khz 3000 + adapter_khz 3000 # Because the hardware cannot be interrogated for the protection state # of sectors, initialize all the sectors to be unprotected. The initial diff --git a/tcl/target/str750.cfg b/tcl/target/str750.cfg index c467ae25..c2fb7869 100644 --- a/tcl/target/str750.cfg +++ b/tcl/target/str750.cfg @@ -19,7 +19,7 @@ if { [info exists CPUTAPID] } { } # jtag speed -jtag_khz 10 +adapter_khz 10 #use combined on interfaces or targets that can't set TRST/SRST separately reset_config trst_and_srst srst_pulls_trst @@ -35,9 +35,9 @@ jtag_ntrst_delay 500 set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi -$_TARGETNAME configure -event reset-start { jtag_khz 10 } +$_TARGETNAME configure -event reset-start { adapter_khz 10 } $_TARGETNAME configure -event reset-init { - jtag_khz 3000 + adapter_khz 3000 # Because the hardware cannot be interrogated for the protection state # of sectors, initialize all the sectors to be unprotected. The initial diff --git a/tcl/target/telo.cfg b/tcl/target/telo.cfg index 0cbdb816..99b9cd69 100644 --- a/tcl/target/telo.cfg +++ b/tcl/target/telo.cfg @@ -26,12 +26,12 @@ reset_config trst_and_srst separate # issue telnet: reset init # issue gdb: monitor reset init $_TARGETNAME configure -event reset-init { - jtag_khz 100 + adapter_khz 100 # this will setup Telo board setupTelo #turn up the JTAG speed - jtag_khz 3000 - puts "JTAG speek now 3MHz" + adapter_khz 3000 + puts "JTAG speed now 3MHz" puts "type helpC100 to get help on C100" } @@ -58,4 +58,4 @@ set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME cfi 0x20000000 0x01000000 2 2 $_TARGETNAME # writing data to memory does not work without this -memwrite burst disable
\ No newline at end of file +memwrite burst disable |