diff options
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/target/davinci.cfg | 127 |
1 files changed, 127 insertions, 0 deletions
diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg index ee840c8d..31750dd5 100644 --- a/tcl/target/davinci.cfg +++ b/tcl/target/davinci.cfg @@ -143,6 +143,133 @@ proc pll_v02_setup {pll_addr mult config} { mww $pll_ctrl_addr $pll_ctrl } +# PLL version 0x03: tested on dm365 +proc pll_v03_setup {pll_addr mult config} { + set pll_ctrl_addr [expr $pll_addr + 0x100] + set pll_secctrl_addr [expr $pll_addr + 0x108] + set pll_ctrl [mrw $pll_ctrl_addr] + + # 1 - power up the PLL + set pll_ctrl [expr $pll_ctrl & ~0x0002] + mww $pll_ctrl_addr $pll_ctrl + + # 2 - clear PLLENSRC (bit 5) + set pll_ctrl [expr $pll_ctrl & ~0x0020] + mww $pll_ctrl_addr $pll_ctrl + + # 2 - clear PLLEN (bit 0) ... enter bypass mode + set pll_ctrl [expr $pll_ctrl & ~0x0001] + mww $pll_ctrl_addr $pll_ctrl + + # 3 - wait at least 4 refclk cycles + sleep 1 + + # 4 - set PLLRST (bit 3) + set pll_ctrl [expr $pll_ctrl | 0x0008] + mww $pll_ctrl_addr $pll_ctrl + + # 5 - wait at least 5 usec + sleep 1 + + # 6 - clear PLLRST (bit 3) + set pll_ctrl [expr $pll_ctrl & ~0x0008] + mww $pll_ctrl_addr $pll_ctrl + + # 9 - optional: write prediv, postdiv, and pllm + mww [expr $pll_addr + 0x0110] [expr ($mult / 2) & 0x1ff] + if { [dict exists $config prediv] } { + set div [dict get $config prediv] + set div [expr ($div - 1)] + mww [expr $pll_addr + 0x0114] $div + } + if { [dict exists $config postdiv] } { + set div [dict get $config postdiv] + set div [expr 0x8000 | ($div - 1)] + mww [expr $pll_addr + 0x0128] $div + } + + # 10 - write start sequence to PLLSECCTL + mww $pll_secctrl_addr 0x00470000 + mww $pll_secctrl_addr 0x00460000 + mww $pll_secctrl_addr 0x00400000 + mww $pll_secctrl_addr 0x00410000 + + # 11 - optional: set plldiv1, plldiv2, ... + # NOTE: this assumes some registers have their just-reset values: + # - PLLSTAT.GOSTAT is clear when we enter + # - ALNCTL has everything set + set aln 0 + if { [dict exists $config div1] } { + set div [dict get $config div1] + set div [expr 0x8000 | ($div - 1)] + mww [expr $pll_addr + 0x0118] $div + set aln [expr $aln | 0x1] + } + if { [dict exists $config div2] } { + set div [dict get $config div2] + set div [expr 0x8000 | ($div - 1)] + mww [expr $pll_addr + 0x011c] $div + set aln [expr $aln | 0x2] + } + if { [dict exists $config div3] } { + set div [dict get $config div3] + set div [expr 0x8000 | ($div - 1)] + mww [expr $pll_addr + 0x0120] $div + set aln [expr $aln | 0x4] + } + if { [dict exists $config div4] } { + set div [dict get $config div4] + set div [expr 0x8000 | ($div - 1)] + mww [expr $pll_addr + 0x0160] $div + set aln [expr $aln | 0x8] + } + if { [dict exists $config div5] } { + set div [dict get $config div5] + set div [expr 0x8000 | ($div - 1)] + mww [expr $pll_addr + 0x0164] $div + set aln [expr $aln | 0x10] + } + if { [dict exists $config div6] } { + set div [dict get $config div6] + set div [expr 0x8000 | ($div - 1)] + mww [expr $pll_addr + 0x0168] $div + set aln [expr $aln | 0x20] + } + if { [dict exists $config div7] } { + set div [dict get $config div7] + set div [expr 0x8000 | ($div - 1)] + mww [expr $pll_addr + 0x016c] $div + set aln [expr $aln | 0x40] + } + if { [dict exists $config div8] } { + set div [dict get $config div8] + set div [expr 0x8000 | ($div - 1)] + mww [expr $pll_addr + 0x0170] $div + set aln [expr $aln | 0x80] + } + if { [dict exists $config div9] } { + set div [dict get $config div9] + set div [expr 0x8000 | ($div - 1)] + mww [expr $pll_addr + 0x0174] $div + set aln [expr $aln | 0x100] + } + if {$aln != 0} { + # write alingment flags + mww [expr $pll_addr + 0x0140] $aln + # write pllcmd.GO; poll pllstat.GO + mww [expr $pll_addr + 0x0138] 0x01 + set pllstat [expr $pll_addr + 0x013c] + while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 } + } + mww [expr $pll_addr + 0x0138] 0x00 + set addr [dict get $config ctladdr] + while {[expr [mrw $addr] & 0x0e000000] != 0x0e000000} { sleep 1 } + + # 12 - set PLLEN (bit 0) ... leave bypass mode + set pll_ctrl [expr $pll_ctrl | 0x0001] + mww $pll_ctrl_addr $pll_ctrl +} + # NOTE: dm6446 requires EMURSTIE set in MDCTL before certain # modules can be enabled. |