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* target: slow targets could cause GDB to time outGary Carlson2010-05-191-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This second half of the patch is proposed to clean up some GDB keep alive issues on arm7_9 targets that start up with very slow clocks. If an attempt is made to write to key registers on the processor with a slow jtag speed, GDB timeout warnings appear on the console (at least mine) when "reset halt" or "reset init" commands are issued from the gdb client: *** BEFORE PATCH *** (gdb) monitor reset init fast memory access is disabled 2 kHz keep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not sent! (1026). Workaround: increase "set remotetimeout" in GDB JTAG tap: at91sam9g20.cpu tap/device found: 0x0792603f (mfg: 0x01f, part: 0x7926, ver: 0x0) target state: halted target halted in ARM state due to breakpoint, current mode: Supervisor cpsr: 0x000000d3 pc: 0x00000000 MMU: disabled, D-Cache: disabled, I-Cache: disabled keep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not sent! (1027). Workaround: increase "set remotetimeout" in GDB keep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not sent! (1006). Workaround: increase "set remotetimeout" in GDB keep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not sent! (1006). Workaround: increase "set remotetimeout" in GDB keep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not sent! (1006). Workaround: increase "set remotetimeout" in GDB keep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not sent! (1004). Workaround: increase "set remotetimeout" in GDB RCLK - adaptive dcc downloads are enabled fast memory access is enabled NAND flash device 'NAND 256MiB 3,3V 8-bit' found (gdb) I added additional keep alive steps in areas that troubleshooting revealed were causing problems. I only did this however for non-fast write memory accesses. I don't think most people would be using fast memory accesses to write to memory when the jtag and system clocks are slow anyway. If you disagree with my feeling, think there is a more elegant way to handle the problem, or think the patch will cause other unforeseen problems with other targets, let me know. As you can see below, the patch does eliminate the problem on my development station and I suspect that it will benefit others. *** AFTER PATCH *** (gdb) monitor reset init fast memory access is disabled 2 kHz JTAG tap: at91sam9g20.cpu tap/device found: 0x0792603f (mfg: 0x01f, part: 0x7926, ver: 0x0) target state: halted target halted in ARM state due to breakpoint, current mode: Supervisor cpsr: 0x000000d3 pc: 0x00000000 MMU: disabled, D-Cache: disabled, I-Cache: disabled RCLK - adaptive dcc downloads are enabled fast memory access is enabled NAND flash device 'NAND 256MiB 3,3V 8-bit' found (gdb) Gary Carlson Gary Carlson, MSEE Principal Engineer Carlson-Minot Inc.
* fix instruction refilling bug when using software breakpoints on a ↵Jun Ma2010-05-121-0/+1
| | | | | | | big-endian arm926ej-s system Signed-off-by: Jun Ma <sync.jma@gmail.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* TARGET/ARM7_9_COMMON: review scope of symbolsAntonio Borneo2010-04-111-14/+14
| | | | | | Add "static" qualifier to private functions. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
* jtag: retire jtag_get/set_end_state()Øyvind Harboe2010-03-191-3/+0
| | | | | | | Voila! This get rids of mysteries about what what state the TAP is in. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* jtag: remove jtag_get_end_state()'s that should be unecessaryØyvind Harboe2010-03-191-1/+1
| | | | | | | | By a bit of code inspection it seems like all of these instances of jtag_get_end_state() can be unambigously replaced by constants. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* jtag: retire one instance of jtag_get_end_state() usageØyvind Harboe2010-03-181-6/+6
| | | | | | Less global variables.... Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* jtag: cut down on usage of unintended modification of global end stateØyvind Harboe2010-03-181-1/+1
| | | | | | | | | | | | | jtag_get/set_end_state() is now deprecated. There were lots of places in the code where the end state was unintentionally modified. The big Q is whether there were any places where the intention was to modify the end state. 0.5 is a long way off, so we'll get a fair amount of testing. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm7/9: remove unused post_restore_contextØyvind Harboe2010-03-171-3/+0
| | | | | | | Unused. If something should happen after context restore, then the calling code can just do it afterwards. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* semihosting: move semihosting cmd to arm cmd groupSpencer Oliver2010-02-281-44/+16
| | | | | | | | | Move semihosting cmd to the arm cmd group. Targets that support semihosting will setup the setup_semihosting callback function. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* ARM: keep a handle to the PCDavid Brownell2010-02-211-19/+23
| | | | | | | | | | | | | | | | Keep a handle to the PC in "struct arm", and use it. This register is used a fair amount, so this is a net minor code shrink (other than some line length fixes), but mostly it's to make things more readable. For XScale, fix a dodgy sequence while stepping. It was initializing a variable to a non-NULL value, then updating it to handle the step-over-active-breakpoint case, and then later testing for non-NULL to see if it should reverse that step-over-active logic. It should have done like ARM7/ARM9 does: init to NULL. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* arm7/9: add nags upon reset about options to improve performanceØyvind Harboe2010-01-201-0/+10
| | | | | | arm7_9 fast_memory_access and working area nags added. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ARM7/ARM9: improved reset supportDavid Brownell2010-01-141-14/+23
| | | | | | | | | | Teach most remaining ARM cores how to use the "reset-assert" event. Same model as elsewhere: iff a handler is provided for that event, use that instead of trying to assert SRST (which may be unavailable, or inappropriate since it resets too much). Else no change. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM7/9 minor cleanupsDavid Brownell2010-01-141-16/+34
| | | | | | | Shrink some overlong lines. Add my 2009 copyright. Move a declaration to the beginning of its block. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* arm7/9: enable check that DCC downloads have been enabledØyvind Harboe2010-01-131-0/+2
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm7/9: add fn to check if dcc downloads have been enabledØyvind Harboe2010-01-131-1/+12
| | | | | | | | DCC downloads should be enabled for any self repecting openocd config file for arm7/9. Print out note about it otherwise. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ARM7/ARM9: help/usage updatesDavid Brownell2010-01-071-8/+8
| | | | | | | | | | | | | | | | | | Provide helptext which was sometimes missing; update some of it to be more accurate. Usage syntax messages have the same EBNF as the User's Guide; there should be no angle brackets in either place. Fix the User's Guide in a few places to be more consistent (mostly to use brackets not parentheses) and to recognize that parameter may be entirely optional (in which case the command just displays output, and changes nothing). Also reference NXP, not Philips, for LPC chips. Don't use "&function"; functions are like arrays, their address is their name. Shrink some overlong lines. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM7_9: Fix segfaultsAntonio Borneo2009-12-301-0/+6
| | | | | | | | | | | Handlers for commands - arm7_9 semihosting <enable | disable> - $_TARGETNAME arp_reset assert 1 didn't check if target has already been examined, and could segfault when using the NULL pointer "arm7_9->eice_cache". Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* arm7_9: Support VINITHI signalAntonio Borneo2009-12-201-23/+0
| | | | | | | | | | | Command "reset halt" checks if PC properly resets, issueing warning: "PC was not 0. Does this target need srst_pulls_trst?". Checking PC against 0 is not always correct. Removed PC value check, as suggested by Øyvind Harboe. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: U-PROPRIET-28D9DF\PROPRIETAIRE <PROPRIETAIRE@propriet-28d9df.(none)>
* target: remove more exit() callsDavid Brownell2009-12-081-8/+0
| | | | | | | | These were all basically "can't happen" cases ... like having state be corrupted by an alpha particle after the previous check for whether a value was in-range. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: move 'extern' decls to *.h filesDavid Brownell2009-12-081-8/+0
| | | | | | | | The exception being declarations for drivers. Those should be split out in some clean way -- like driver add/remove calls made by initialization code -- but that's for another day. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: use <target/arm.h> not armv4_5.hDavid Brownell2009-12-071-0/+1
| | | | | | | | | | | | | | Move most declarations in <target/armv4_5.h> to <target/arm.h> and update users. What's left in the older file is stuff that I think should be removed ... the old register cache access stuff, which makes it awkward to support microcontroller profile (Cortex-M) cores. The armv4_5_run_algorithm() declaration was moved too, even though it's not yet as generic as it probably ought to be. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename some generic routinesDavid Brownell2009-12-071-1/+2
| | | | | | | | | | | | | | | | Rename some (mostly) generic ARM functions: armv4_5_arch_state() --> arm_arch_state() armv4_5_get_gdb_reg_list() --> arm_get_gdb_reg_list() armv4_5_init_arch_info() --> arm_init_arch_info() Cores using the microcontroller profile may want a different arch_state() routine though. (Also fix strange indentation in arm_arch_state: use tabs only! And update a call to it, removing assignment-in-conditional.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM semihosting: use breakpoint on ARM7Nicolas Pitre2009-12-041-7/+9
| | | | | | | | | | | | Fall back to software breakpoint when vector catch isn't available. Possible enhancements: - add extra optional command parameter to select high vectors - add extra optional command parameter to select hardware breakpoint Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename armv4_5_algorithm as arm_algorithmDavid Brownell2009-12-041-1/+1
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: ARMV4_5_COMMON_MAGIC --> ARM_COMMON_MAGICDavid Brownell2009-12-041-1/+1
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename armv4_5_mode_* AS arm_mode_*David Brownell2009-12-041-3/+3
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename ARMV4_5_MODE_* as ARM_MODE_*David Brownell2009-12-041-17/+17
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename ARMV4_5_STATE_* as ARM_STATE_*David Brownell2009-12-041-15/+15
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: remove semihosting globalsDavid Brownell2009-12-041-6/+16
| | | | | | | | Store a flag and errno in in "struct arm". Have "poll" output report when semihosting is active. Shrink some of the affected lines. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* basic ARM semihosting supportNicolas Pitre2009-12-031-0/+44
| | | | | | | | | | | | | | | | | | | | Semihosting enables code running on an ARM target to use the I/O facilities on the host computer. The target application must be linked against a library that forwards operation requests by using the SVC instruction that is trapped at the Supervisor Call vector by the debugger. The "hosted" library version provided with CodeSourcery's Sourcery G++ Lite for ARM EABI is one example. This is currently available for ARM9 processors, but any ARM variant should be able to support this with little additional work. Tested using binaries compiled with Sourcery G++ Lite 2009q1-161 and ARM RVCT 3.0. [dbrownell@users.sourceforge.net: doc tweaks, NEWS] Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* change #include "time_support.h" to <helper/time_support.h>Zachary T Welch2009-12-031-1/+1
| | | | | | | | | | | | Changes from the flat namespace to heirarchical one. Instead of writing: #include "time_support.h" the following form should be used. #include <helper/time_support.h> The exception is from .c files in the same directory.
* target: uplevel add_{break,watch}point() error checksDavid Brownell2009-11-281-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | In target_type.h it's documented that the target must be halted for add_breakpoint() ... and with slight ambiguity, also for its add_watchpoint() sibling. So rather than verifying that constraint in the CPU drivers, do it in the target_add_{break,watch}point() routines. Add minor paranoia on the remove_*point() paths too: save the return value, and print it out in in the LOG_DEBUG message in case it's nonzero. Note that with some current cores, like all ARMv7 ones I've looked at, there's no technical issue preventing watchpoint or breakpoint add/remove operations on active cores. This model seems deeply wired into OpenOCD though. ALSO: the ARM targets were fairly "good" about enforcing that constraint themselves. The MIPS ones were relied on other code to catch such stuff, but it's not clear such code existed ... keep an eye out for new issues on MIPS. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM7/9: shrink run_algorithm_inner() linesDavid Brownell2009-11-251-2/+10
| | | | | | 300+ characters is unreasonable. So is half that. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* remove target_type register_command callbackZachary T Welch2009-11-241-8/+7
| | | | | | Uses chaining of command_registration structures to eliminate all target_type register_callback routines. Exports the command_handler registration arrays for those target types that are used by others.
* arm7_9_common: use register_commands()Zachary T Welch2009-11-241-20/+37
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* use COMMAND_REGISTER macroZachary T Welch2009-11-241-4/+4
| | | | | Replaces direct calls to register_command() with a macro, to allow its parameters to be changed and callers updated in phases.
* ARM: use arm_reg_current()David Brownell2009-11-221-19/+26
| | | | | | | | | | Start using the arm_reg_current() call. This shrinks and speeds the affected code. It can also prevent some coredumps coming from invalid CPSR values ... the ARMV4_5_CORE_REG_MODE() macro returns bogus registers if e.g. "Secure Monitor" mode isn't supported by the current CPU. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: remove 'armv4_5_common_s' migration #defineDavid Brownell2009-11-221-11/+11
| | | | | | Finish migrating from the old symbol to the new one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: arm_set_cpsr() handles T and J bitsDavid Brownell2009-11-221-11/+21
| | | | | | | | | | | | | | Have arm_set_cpsr() handle the two core state flags, updating the CPU state. This eliminates code in various debug_entry() paths, and marginally improves handling of the J bit. Catch and comment a few holes in the handling of the J bit on ARM926ejs cores ... it's unlikely our users will care about Jazelle mode, but we can at least warn of Impending Doom. If anyone does use it, these breadcrumbs may help them to find the right path through the code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: define two register utilitiesDavid Brownell2009-11-221-10/+8
| | | | | | | | | | | | | | Define arm_reg_current() ... returning handle to a given register, and encapsulating the current mode's register shadowing. It's got one current use, for reporting the current register set to GDB. This will let later patches clean up much ARMV4_5_CORE_REG_MODE() nastiness, saving a bit of code. Define and use arm_set_cpsr() ... initially it updates the cached CPSR and sets up state used by arm_reg_current(), plus any SPSR handle. (Later: can also set up for T and J bits.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: simplify CPSR handlingDavid Brownell2009-11-221-22/+37
| | | | | | | | | | | | | | Stash a pointer to the CPSR in the "struct arm", to help get rid of the (common) references to its index in the register cache. This removes almost all references to CPSR offsets outside of the toplevel ARM code ... except a pair related to the current ARM11 "simulator" logic (which should be removable soonish). This is a net minor code shrink of a few hundred bytes of object code, and also makes the code more readable. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: pass 'struct reg *' to register r/w routinesDavid Brownell2009-11-201-24/+18
| | | | | | | | | | | | | | | | Implementations need to access the register struct they modify; make it easier and less error-prone to identify the instance. (This removes over 10% of the ARMV4_5_CORE_REG_MODE nastiness...) Plus some minor fixes noted when making these updates: ARM7/ARM9 accessor methods should be static; don't leave CPSR wrongly marked "dirty"; note significant XScale omissions in register handling; and have armv4_5_build_reg_cache() record its result. Rename "struct armv4_5_core_reg" as "struct arm_reg"; it's used for more than those older architecture generations. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM7/ARM9: remove old "debug commands"David Brownell2009-11-201-130/+0
| | | | | | | | | | | | | | | Remove two commands that were documented as "debug commands" and where "you probably don't want to use this". We never intended to support them, and at least one problem report boiled down to using this when it shouldn't have been used. Update the docs on the existing register commands to talk a bit more about register access and cache behavior. (Those debug commands existed largely to *bypass* the cache.) And fix some minor doc goofs that snuck in with recent changes, renaming "armv4_5" as "arm" and "arm9tdmi" as "arm9". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: create/use register_cache_invalidate()David Brownell2009-11-191-7/+4
| | | | | | | | | | | | | | | Create a generic register_cache_invalidate(), and use it to replace three all-but-identical core-specific routines: - armv4_5_invalidate_core_regs() - armv7m_invalidate_core_regs - mips32_invalidate_core_regs() too. Make cache->num_regs be unsigned, avoiding various errors. Net code shrink and simplification. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* remove fast command and jim_global_longZachary T Welch2009-11-181-2/+2
| | | | | | | | Removing the fast command eliminates the fast_and_dangerous global, which was used only by arm7_9_common as an initializer. The command is not called in the tree; instead, more explicit commands are used. The jim_global_long function was not used anywhere in the tree.
* use COMMAND_PARSE_ENABLE macro where appropriateZachary T Welch2009-11-181-42/+3
| | | | | | | | Updates all command parsing of simple "enable" and "disable" arguments. A few case in the tree use a tri-state or extended arguments, which cannot use this simple macro. Simlifies the xscale icache/dcache command handler logic.
* ARM: add is_arm_mode()David Brownell2009-11-171-16/+7
| | | | | | | | | | | | | | | | | | Add a new is_arm_mode() predicate, and use it to replace almost all calls to current armv4_5_mode_to_number(). Eventually those internal mode numbers should vanish... along with their siblings in the armv7a.c file. Remove a handful of superfluous checks ... e.g. the mode number was just initialized, or (debug entry methods) already validated. Move one of the macros using internal mode numbers into the only file which uses that macro. Make the tables manipulated with those numbers be read-only and, where possible, static so they're not confused with part of the generic ARM interface. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add arm_mode_name()David Brownell2009-11-171-3/+8
| | | | | | | | | | | | | | | Add and use arm_mode_name() to map from PSR bits to user meaningful names. It uses a new table which, later, can be used to hold other mode-coupled data. Add definitions for the "Secure Monitor" mode, as seen on some ARM11 cores (like ARM1176) and on Cortex-A8. The previous mode name scheme didn't understand that mode. Remove the old mechanism ... there were two copies, caused by Cortex-A8 needing to add "Secure Monitor" mode support. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* command_handler: change 'cmd_ctx' to CMD_CTXZachary T Welch2009-11-171-24/+24
| | | | Convert all command handler 'cmd_ctx' parameter usage with CMD_CTX.
* command_handler: change 'args' to CMD_ARGVZachary T Welch2009-11-171-14/+14
| | | | | This patch converts all instances of 'args' in COMMAND_HANDLER routines to use CMD_ARGV macro.
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