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* ARM: rename armv4_5_build_reg_cache() as arm_*()David Brownell2009-12-041-1/+1
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename armv4_5_mode_* AS arm_mode_*David Brownell2009-12-041-9/+9
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename ARMV4_5_MODE_* as ARM_MODE_*David Brownell2009-12-041-25/+25
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename ARMV4_5_STATE_* as ARM_STATE_*David Brownell2009-12-041-6/+6
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: cygwin build fixesDavid Brownell2009-12-041-2/+6
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* doxygen: remove some warningsDavid Brownell2009-12-031-0/+1
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM DPM: share debug reason logicDavid Brownell2009-12-031-0/+36
| | | | | | | | | | | | | | | | | | No point in both ARM11 and Cortex-A8 having private copies of the logic sorting out e.g. DBG_REASON_WATCHPOINT. Add and use a shared routine for this ... there's actually a bunch more debug entry logic that could be shared, this is just a start on that. Note that this routine fixes a bug observed in the ARM11 code, where some abort mode quirks were displayed as being an unknown debug reason; and also silences needless ARM11 chatter. Likewise with private copies of DSCR ... add one to the DPM struct. Save it as part of setting DBG_REASON_* so later patches can switch over to using that copy. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* change #include "jtag.h" to <jtag/jtag.h>Zachary T Welch2009-12-031-1/+1
| | | | | | | | | | | | Changes from the flat namespace to heirarchical one. Instead of writing: #include "jtag.h" the following form should be used. #include <jtag/jtag.h> The exception is from .c files in the same directory.
* ARM DPM: tweak initializationDavid Brownell2009-12-021-13/+12
| | | | | | Move the initial breakpoint/watchpoint disable calls to arm_dpm_initialize(), and start using that routine. This split helps with arm11 support.
* ARMv7a/Cortex-A8: report watchpoint trigger insnDavid Brownell2009-12-021-0/+17
| | | | | | | | | | | Save and display the address of the instruction which triggered the watchpoint. Because of pipelining, that's well behind the PC value when debug entry completes. (Example in a subroutine that had been returned from...) Remove unused A8 stuff, mostly watchpoint hooks from the header. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: core DPM support for watchpointsDavid Brownell2009-12-011-2/+242
| | | | | | | | | | | | | | | | | | | | | This is a NOP unless the underlying core exposes two new methods, and neither of the two cores using this (ARM11xx, Cortex-A8) do so yet. This patch only updates those cores so they pass a flag saying whether or not to update breakpoint and watchpoint status before resuming; and removing some now-needless anti-segfault code from ARM11. Cortex-A8 didn't have that code ... yes, it segfaulted when setting watchpoints. NOTE: this uses a slightly different strategy for setting/clearing breakpoints than the ARM7/ARM9/etc code uses. It leaves them alone unless it's *got* to change something, to speed halt/resume cycles (including single stepping). ALSO NOTE: this under-delivers for Cortex-A8, where regions with size up to 2 GBytes can be watched ... it handles watchpoints which ARM11 can also handle (size 1/2/4 bytes). Should get fixed later. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: implement mrc()/mcr() as DPM opsDavid Brownell2009-12-011-0/+59
| | | | | | | | | | | | | Instead of having separate ARM11 and Cortex-A8 implementations of this code, have one shared implementation which just builds on the existing "run instruction via R0" support. This enables followup patches to remove that now-unused code from those two drivers. (Patches to move the "mrc" and "mcr" code into "struct arm" are due too ... MIPS and other cores do not support those ARM-specific concepts.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: implement DPMDavid Brownell2009-11-241-9/+4
| | | | | | | | This implements the DPM interface for Cortex-A8 cores. It also adds a synchronization operation to the DPM framework, which is needed by the Cortex-A8 after CPSR writes. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: new DPM interfaceDavid Brownell2009-11-241-0/+529
First version of interface for sharing code between ARMv6 and ARMv7a debug modules ... now the architecture includes debug support. (Not the same as for the trimmed-down v7m or v6m though!) This is a first version of an interface that will let the ARM11 and Cortex-A8 support share code, features, and bugfixes. Based on existing code from both of those cores. The ARM v7-AR architecture specification calls this commonality the "Debug Programmer's Model (DPM)", which seemed to be an appropriate acronym -- a TLA even! -- for use in our code. Made it so. :) The initial scope of this just supports register access, and is geared towards supporting top level "struct arm" mechanisms. Later, things like breakpoint and watchpoint support should be included. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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