| Commit message (Collapse) | Author | Age | Files | Lines |
|---|
| |
|
|
|
|
| |
- add comment where to find the various loaders src files.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
|
| |
|
|
|
|
|
| |
when an unknown core mode is read from the target,
report error. Can be communication failure.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
| |
|
|
|
|
|
| |
Update the arm_checksum_memory and arm_blank_check_memory
algorithms to use a breakpoint instruction on v5 arch.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
|
| |
Various commands, e.g. "arm mcr xxxx" would fail if invoked upon startup
since it there was no command context defined for the jim interpreter
in that case.
A Jim interpreter is now associated with a command context(telnet,
gdb server's) or the default global command context.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
| |
|
|
|
|
| |
Add "static" qualifier to private data.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
|
| |
|
|
|
|
|
| |
core_type check is not required as the core function will be
null for cores that do not support the mcr/mrc functions.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
| |
Move semihosting cmd to the arm cmd group.
Targets that support semihosting will setup the
setup_semihosting callback function.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
|
| |
|
|
|
|
|
|
| |
- Add arm cmd group to armv7m cmd chain.
- arm cmd's now check the core type before running a cmd.
- todo: add support for armv7m registers for reg cmd.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Keep a handle to the PC in "struct arm", and use it.
This register is used a fair amount, so this is a net
minor code shrink (other than some line length fixes),
but mostly it's to make things more readable.
For XScale, fix a dodgy sequence while stepping. It
was initializing a variable to a non-NULL value, then
updating it to handle the step-over-active-breakpoint
case, and then later testing for non-NULL to see if
it should reverse that step-over-active logic. It
should have done like ARM7/ARM9 does: init to NULL.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This sets up a few of the core "struct arm" data structures so they
can be used with ARMv7-M cores. Specifically, it:
- defines new ARM core_modes to match the microcontroller modes
(e.g. HANDLER not IRQ, and two types of thread mode);
- Establishes a new microcontroller "core_type", which can be
used to make sure v7-M (and v6-M) cores are handled right;
- adds "struct arm" to "struct armv7m" and arranges for the
target_to_armv7m() converter to use it;
- sets up the arm.core_cache and arm.cpsr values
- makes the Cortex-M3 code maintain arm.map and arm.core_mode.
This is currently set up as a parallel data structure, primarily to
minimize special cases for the semihosting support with microcontroller
profile cores.
Later patches can rip out the duplicative ARMv7-M support and start
reusing core ARM code.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
|
|
| |
Usage syntax messages have the same EBNF as the User's Guide;
there should be no angle brackets in either place.
Uupdate some helptext to be more accurate.
Don't use "&function"; functions are like arrays, their address
is their name.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
| |
Provide and use debug_reason_name() instead of expecting targets
to call Jim_Nvp_value2name_simple(). Less dependency on Jim, and
the code becomes more clear too.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Move most declarations in <target/armv4_5.h> to <target/arm.h>
and update users.
What's left in the older file is stuff that I think should be
removed ... the old register cache access stuff, which makes it
awkward to support microcontroller profile (Cortex-M) cores.
The armv4_5_run_algorithm() declaration was moved too, even
though it's not yet as generic as it probably ought to be.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Rename some (mostly) generic ARM functions:
armv4_5_arch_state() --> arm_arch_state()
armv4_5_get_gdb_reg_list() --> arm_get_gdb_reg_list()
armv4_5_init_arch_info() --> arm_init_arch_info()
Cores using the microcontroller profile may want a different
arch_state() routine though.
(Also fix strange indentation in arm_arch_state: use tabs only!
And update a call to it, removing assignment-in-conditional.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
| |
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
| |
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
| |
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
| |
And remove that old symbol.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
| |
And make arm_state_strings[] be const.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
| |
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
| |
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
| |
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
| |
Store a flag and errno in in "struct arm".
Have "poll" output report when semihosting is active.
Shrink some of the affected lines.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
|
|
| |
Changes from the flat namespace to heirarchical one. Instead of writing:
#include "binarybuffer.h"
the following form should be used.
#include <helper/binarybuffer.h>
The exception is from .c files in the same directory.
|
| |
|
|
|
|
|
|
|
|
|
| |
Except for USR/SYS mode, the labels for the shadowed SP and LR
registers were reversed. LR is r14; SP is r13. Fix.
This would not affect GDB users; GDB references are positional.
Only folk working directly with OpenOCD register values would
have noticed this bug.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Switch "mrc" and "mcr" commands to be toplevel ARM operations,
as they should initially have been.
Correct the usage message for both commands: it matches ARM
documentation (as one wants!) instead of reordering them to
match the funky mrc() and mcr() method usage (sigh).
For Cortex-A8: restore a line that got accidentally dropped,
so the secure monitor mode shadow registers will show again.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
| |
Lines of 300+ characters are still bad; debug tweaks.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
| |
Uses chaining of command_registration structures to eliminate all
target_type register_callback routines. Exports the command_handler
registration arrays for those target types that are used by others.
|
| | |
|
| |
|
|
|
| |
Replaces direct calls to register_command() with a macro, to allow
its parameters to be changed and callers updated in phases.
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
First version of interface for sharing code between ARMv6 and ARMv7a
debug modules ... now the architecture includes debug support. (Not
the same as for the trimmed-down v7m or v6m though!) This is a first
version of an interface that will let the ARM11 and Cortex-A8 support
share code, features, and bugfixes. Based on existing code from both
of those cores.
The ARM v7-AR architecture specification calls this commonality the
"Debug Programmer's Model (DPM)", which seemed to be an appropriate
acronym -- a TLA even! -- for use in our code. Made it so. :)
The initial scope of this just supports register access, and is geared
towards supporting top level "struct arm" mechanisms. Later, things
like breakpoint and watchpoint support should be included.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
| |
Finish migrating from the old symbol to the new one.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Have arm_set_cpsr() handle the two core state flags, updating
the CPU state. This eliminates code in various debug_entry()
paths, and marginally improves handling of the J bit.
Catch and comment a few holes in the handling of the J bit on
ARM926ejs cores ... it's unlikely our users will care about
Jazelle mode, but we can at least warn of Impending Doom. If
anyone does use it, these breadcrumbs may help them to find
the right path through the code.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Define arm_reg_current() ... returning handle to a given register,
and encapsulating the current mode's register shadowing. It's got
one current use, for reporting the current register set to GDB.
This will let later patches clean up much ARMV4_5_CORE_REG_MODE()
nastiness, saving a bit of code.
Define and use arm_set_cpsr() ... initially it updates the cached
CPSR and sets up state used by arm_reg_current(), plus any SPSR
handle. (Later: can also set up for T and J bits.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Stash a pointer to the CPSR in the "struct arm", to help get rid
of the (common) references to its index in the register cache.
This removes almost all references to CPSR offsets outside of the
toplevel ARM code ... except a pair related to the current ARM11
"simulator" logic (which should be removable soonish).
This is a net minor code shrink of a few hundred bytes of object
code, and also makes the code more readable.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Implementations need to access the register struct they modify;
make it easier and less error-prone to identify the instance.
(This removes over 10% of the ARMV4_5_CORE_REG_MODE nastiness...)
Plus some minor fixes noted when making these updates: ARM7/ARM9
accessor methods should be static; don't leave CPSR wrongly marked
"dirty"; note significant XScale omissions in register handling;
and have armv4_5_build_reg_cache() record its result.
Rename "struct armv4_5_core_reg" as "struct arm_reg"; it's used
for more than those older architecture generations.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Create a generic register_cache_invalidate(), and use it to
replace three all-but-identical core-specific routines:
- armv4_5_invalidate_core_regs()
- armv7m_invalidate_core_regs
- mips32_invalidate_core_regs() too.
Make cache->num_regs be unsigned, avoiding various errors.
Net code shrink and simplification.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
| |
Just pre-allocate memory for the cached register value.
Shrinks heap overhead; increases locality-of-reference.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
| |
Combine register names with other per-register data into a
single template structure. This saves space, and makes it
easier to change how registers get handled (by shrinking
the number of places that care about cache indices).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
We don't want an ARMv7-specific core state enumeration just to
add ThumbEE state. Update the generic stuff to handle that,
and replace the V7-specific bits with it.
For Cortex-A8: on debug entry, check both the T and J bits
instead of just the T bit. When the J bit is set, set the
right state and warn appropriately.
(And while we're at it, move the generic arm struct to the front
of the v7a structure, for somewhat better code generation.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Change the layout to show the "Secure Monitor" registers too,
when they're present.
Instead of lining registers for each of six (or seven) modes up
in adjacent vertical columns, display each mode's registers (or
shadows) in a single block, avoiding duplicate value displays.
This also lets us shrink the line length to fits in standard 80
character lines ... six or seven 18-character columns can't fit.
Relabel "r13" as "sp", so it's more meaningful.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
|
|
| |
If the core doesn't provide an optimized version of this
method, provide one without core-specific optimizations.
Use this to make Cortex-A8 support the "arm reg" command.
Related: make the two register access methods properly static,
have the "set" log a "not halted" error too, and make sure
that the "valid" flag is set on successful reads.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
Teach the "armv4_5" register code to understand about the
secure monitor mode:
- Add the other three shadowed registers to the arrays
- Support another internal mode number (sigh) in mappings
- Catch malloc/calloc failures building that register cache
This should kick in for Cortex-A8 and ARM1176.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
| |
It's used to flag cores with the "TrustZone" extension,
and is used in subsequent patches to set up support for
the registers shadowed by its new secure monitor mode.
The ARM1176 and Cortex-A8 both support this new mode.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add a new is_arm_mode() predicate, and use it to replace almost
all calls to current armv4_5_mode_to_number().
Eventually those internal mode numbers should vanish... along
with their siblings in the armv7a.c file.
Remove a handful of superfluous checks ... e.g. the mode number
was just initialized, or (debug entry methods) already validated.
Move one of the macros using internal mode numbers into the only
file which uses that macro. Make the tables manipulated with
those numbers be read-only and, where possible, static so they're
not confused with part of the generic ARM interface.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add and use arm_mode_name() to map from PSR bits to user
meaningful names. It uses a new table which, later, can
be used to hold other mode-coupled data.
Add definitions for the "Secure Monitor" mode, as seen on
some ARM11 cores (like ARM1176) and on Cortex-A8. The
previous mode name scheme didn't understand that mode.
Remove the old mechanism ... there were two copies, caused
by Cortex-A8 needing to add "Secure Monitor" mode support.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
All ARM cores need to provide obsolete FPA registers in their
GDB register dumps. (Even though cores with floating point
support now generally use some version of VFP...)
Clean up that support a bit by sharing the same dummy registers,
and removing the duplicate copies. Eventually we shouldn't need
to export those dummies.
(This makes the ARMv7-M support include the armv4_5 header, and
cleans up related #includes, but doesn't yet use anything from
there except those dummies.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
| |
|
|
| |
Convert all command handler 'cmd_ctx' parameter usage with CMD_CTX.
|
| |
|
|
|
| |
This patch converts all instances of 'args' in COMMAND_HANDLER routines
to use CMD_ARGV macro.
|
| |
|
|
|
| |
This patch converts all instances of 'argc' in COMMAND_HANDLER routines
to use CMD_ARGC.
|
