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* ARM: rename some generic routinesDavid Brownell2009-12-071-2/+2
| | | | | | | | | | | | | | | | Rename some (mostly) generic ARM functions: armv4_5_arch_state() --> arm_arch_state() armv4_5_get_gdb_reg_list() --> arm_get_gdb_reg_list() armv4_5_init_arch_info() --> arm_init_arch_info() Cores using the microcontroller profile may want a different arch_state() routine though. (Also fix strange indentation in arm_arch_state: use tabs only! And update a call to it, removing assignment-in-conditional.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: move opcode macros to <target/arm_opcodes.h>David Brownell2009-12-071-0/+1
| | | | | | | | | | | | | | | Move the ARM opcode macros from <target/armv4_5.h>, and a few Thumb2 ones from <target/armv7m.h>, to more appropriate homes in a new <target/arm_opcodes.h> file. Removed duplicate opcodes from that v7m/Thumb2 set. Protected a few macro argument references by adding missing parentheses. Tightening up some of the line lengths turned up a curious artifact: the macros for the Thumb opcodes are all 32 bits wide, not 16 bits. There's currently no explanation for why it's done that way... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename ARMV4_5_STATE_* as ARM_STATE_*David Brownell2009-12-041-4/+4
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM DPM: share debug reason logicDavid Brownell2009-12-031-25/+12
| | | | | | | | | | | | | | | | | | No point in both ARM11 and Cortex-A8 having private copies of the logic sorting out e.g. DBG_REASON_WATCHPOINT. Add and use a shared routine for this ... there's actually a bunch more debug entry logic that could be shared, this is just a start on that. Note that this routine fixes a bug observed in the ARM11 code, where some abort mode quirks were displayed as being an unknown debug reason; and also silences needless ARM11 chatter. Likewise with private copies of DSCR ... add one to the DPM struct. Save it as part of setting DBG_REASON_* so later patches can switch over to using that copy. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM DPM: make DSCR bit defs sharableDavid Brownell2009-12-031-23/+29
| | | | | | | | | | | | | | | | Move the symbols for these bits from "armv7a.h" to "arm_dpm.h", where they can be seen and used not just by Cortex-A but also by the ARM11 (armv6) code. Change them from bit numbers to bit masks ... this matches the usage in ARM11 code, and also makes it easier to read. Rename DSCR_EXT_INT_EN as DSCR_ITR_EN to match the docs; it's enabling ITR functionality, not external interrupts, so this changes the name to be less misleading. (There *IS* a bit affecting interrupts, and this isn't it.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM DPM: tweak initializationDavid Brownell2009-12-021-1/+6
| | | | | | Move the initial breakpoint/watchpoint disable calls to arm_dpm_initialize(), and start using that routine. This split helps with arm11 support.
* ARMv7a/Cortex-A8: report watchpoint trigger insnDavid Brownell2009-12-021-22/+8
| | | | | | | | | | | Save and display the address of the instruction which triggered the watchpoint. Because of pipelining, that's well behind the PC value when debug entry completes. (Example in a subroutine that had been returned from...) Remove unused A8 stuff, mostly watchpoint hooks from the header. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: basic watchpoint supportDavid Brownell2009-12-011-0/+66
| | | | | | | Actually this should handle both breakpoints and watchpoints ... but the DPM framework only handles watchpoints for now. Works on Beagle. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: core DPM support for watchpointsDavid Brownell2009-12-011-8/+4
| | | | | | | | | | | | | | | | | | | | | This is a NOP unless the underlying core exposes two new methods, and neither of the two cores using this (ARM11xx, Cortex-A8) do so yet. This patch only updates those cores so they pass a flag saying whether or not to update breakpoint and watchpoint status before resuming; and removing some now-needless anti-segfault code from ARM11. Cortex-A8 didn't have that code ... yes, it segfaulted when setting watchpoints. NOTE: this uses a slightly different strategy for setting/clearing breakpoints than the ARM7/ARM9/etc code uses. It leaves them alone unless it's *got* to change something, to speed halt/resume cycles (including single stepping). ALSO NOTE: this under-delivers for Cortex-A8, where regions with size up to 2 GBytes can be watched ... it handles watchpoints which ARM11 can also handle (size 1/2/4 bytes). Should get fixed later. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: remove previous mcr()/mrc() methodsDavid Brownell2009-12-011-97/+1
| | | | | | | | We don't need this code, now that the DPM code handles it. Neither do we need the ARMv7-A CP15 operations; remove their remnants too. And disable a mostly-needless diagnostic. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: "mcr" and "mrc" are ARM-specificDavid Brownell2009-12-011-5/+6
| | | | | | | | | | | | | | Switch "mrc" and "mcr" commands to be toplevel ARM operations, as they should initially have been. Correct the usage message for both commands: it matches ARM documentation (as one wants!) instead of reordering them to match the funky mrc() and mcr() method usage (sigh). For Cortex-A8: restore a line that got accidentally dropped, so the secure monitor mode shadow registers will show again. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: stop using CP15 opsDavid Brownell2009-12-011-16/+53
| | | | | | | | | | | | | | | | | | | | | There were two chunks of Cortex-A8 code which called the ARMv7-A CP15 operations; get rid of them, helping prepare to remove those methods completely: - post_debug_entry() can use the mrc() method to read its two registers. - write_memory() can use dpm->instr_write_data_r0() to flush the ICache and DCache ... doing it this way is actually faster since it reduces per-write overhead. Note that the mrc() method parameters are re-ordered with respect to the ARM instruction documentation, so that part can be confusing. Cleaned up the layout and comments in those areas a bit. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: support "reset-assert" eventDavid Brownell2009-11-271-5/+28
| | | | | | | | | | | | | | Use the new "reset-assert" event; else SRST; else fail. Tested on an OMAP3, using the event. NOTE: still doesn't handle "reset halt". For some reason neither VCR nor PRCR seemed effective; they held the value that was written, but VCR didn't trigger debug entry when the reset vector fired (maybe the vector needs configuring?) and PRCR refused to hold the chip in reset until deassert() could force the core into debug state. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* remove target_type register_command callbackZachary T Welch2009-11-241-8/+7
| | | | | | Uses chaining of command_registration structures to eliminate all target_type register_callback routines. Exports the command_handler registration arrays for those target types that are used by others.
* cortex_a8: use register_commands()Zachary T Welch2009-11-241-17/+25
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* use COMMAND_REGISTER macroZachary T Welch2009-11-241-3/+3
| | | | | Replaces direct calls to register_command() with a macro, to allow its parameters to be changed and callers updated in phases.
* Cortex-A8: avoid DSCR readsDavid Brownell2009-11-241-48/+103
| | | | | | | | | | | | | | | | | There was a lot of needless handshaking overhead in the current Cortex-A8 DCC/ITR operations, since the status read by each step was discarded rather than letting the next step know it. This shrinks the handshaking by: (a) passing status along from previous steps, avoiding re-fetching; which enables the big win (b) relying on a useful invariant: that the DSCR_INSTR_COMP bit is set after every call to a DPM method. A "reg sp_usr" call previously took 17 flushes; now it takes just 9. This visibly speeds common operations like entry to debug state and stepping, as well as "arm reg" and so on. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: hook up DPMDavid Brownell2009-11-241-323/+35
| | | | | | | | | This replaces two versions of register access functions. One was commented out, and seemed to have uncertain intent. The other was fairly new, and helped motivate the DPM framework once I observed that the ARM11 was doing the very same ops. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: implement DPMDavid Brownell2009-11-241-0/+167
| | | | | | | | This implements the DPM interface for Cortex-A8 cores. It also adds a synchronization operation to the DPM framework, which is needed by the Cortex-A8 after CPSR writes. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: minor cleanupDavid Brownell2009-11-241-21/+33
| | | | | | | | Make various functions static, add some comments, report vector catch as a flavor of DBG_REASON_BREAKPOINT, get rid of needless/undesirable ARMV4_5_CORE_REG_MODE, etc. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: use arm_reg_current()David Brownell2009-11-221-16/+8
| | | | | | | | | | Start using the arm_reg_current() call. This shrinks and speeds the affected code. It can also prevent some coredumps coming from invalid CPSR values ... the ARMV4_5_CORE_REG_MODE() macro returns bogus registers if e.g. "Secure Monitor" mode isn't supported by the current CPU. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: remove 'armv4_5_common_s' migration #defineDavid Brownell2009-11-221-8/+8
| | | | | | Finish migrating from the old symbol to the new one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: arm_set_cpsr() handles T and J bitsDavid Brownell2009-11-221-23/+0
| | | | | | | | | | | | | | Have arm_set_cpsr() handle the two core state flags, updating the CPU state. This eliminates code in various debug_entry() paths, and marginally improves handling of the J bit. Catch and comment a few holes in the handling of the J bit on ARM926ejs cores ... it's unlikely our users will care about Jazelle mode, but we can at least warn of Impending Doom. If anyone does use it, these breadcrumbs may help them to find the right path through the code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: define two register utilitiesDavid Brownell2009-11-221-6/+1
| | | | | | | | | | | | | | Define arm_reg_current() ... returning handle to a given register, and encapsulating the current mode's register shadowing. It's got one current use, for reporting the current register set to GDB. This will let later patches clean up much ARMV4_5_CORE_REG_MODE() nastiness, saving a bit of code. Define and use arm_set_cpsr() ... initially it updates the cached CPSR and sets up state used by arm_reg_current(), plus any SPSR handle. (Later: can also set up for T and J bits.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: simplify CPSR handlingDavid Brownell2009-11-221-7/+5
| | | | | | | | | | | | | | Stash a pointer to the CPSR in the "struct arm", to help get rid of the (common) references to its index in the register cache. This removes almost all references to CPSR offsets outside of the toplevel ARM code ... except a pair related to the current ARM11 "simulator" logic (which should be removable soonish). This is a net minor code shrink of a few hundred bytes of object code, and also makes the code more readable. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: pass 'struct reg *' to register r/w routinesDavid Brownell2009-11-201-24/+23
| | | | | | | | | | | | | | | | Implementations need to access the register struct they modify; make it easier and less error-prone to identify the instance. (This removes over 10% of the ARMV4_5_CORE_REG_MODE nastiness...) Plus some minor fixes noted when making these updates: ARM7/ARM9 accessor methods should be static; don't leave CPSR wrongly marked "dirty"; note significant XScale omissions in register handling; and have armv4_5_build_reg_cache() record its result. Rename "struct armv4_5_core_reg" as "struct arm_reg"; it's used for more than those older architecture generations. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: better context restoreDavid Brownell2009-11-191-13/+67
| | | | | | | The previous version never wrote dirty registers for non-current CPU modes ... fix that. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: mode supportDavid Brownell2009-11-191-30/+116
| | | | | | | | | | | | | | | | We *should* be able to read and write registers in any core mode, instead of being stuck with whatever mode the core was when we entered debug state. This patch makes them work. Note that the current restore_context() only handles the current mode; writing to other-mode registers is a NOP without a followup patch fixing that. Also, that SPSR access needed some bugfixes; it was confused with CPSR. Secure monitor mode also seems dubious; there's probably more to be done before that's sufficiently understood by the debugger. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: create/use register_cache_invalidate()David Brownell2009-11-191-2/+3
| | | | | | | | | | | | | | | Create a generic register_cache_invalidate(), and use it to replace three all-but-identical core-specific routines: - armv4_5_invalidate_core_regs() - armv7m_invalidate_core_regs - mips32_invalidate_core_regs() too. Make cache->num_regs be unsigned, avoiding various errors. Net code shrink and simplification. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: parts of examine() run just onceDavid Brownell2009-11-191-4/+15
| | | | | | | | | The examine() method has some conceptual breakage. Cope with it by manually splitting out the run-once parts from the after-each-reset parts ... this gets rid of memory leaks and speeds up resets after the first one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-A: use standard ARM core statesDavid Brownell2009-11-191-12/+38
| | | | | | | | | | | | | | | We don't want an ARMv7-specific core state enumeration just to add ThumbEE state. Update the generic stuff to handle that, and replace the V7-specific bits with it. For Cortex-A8: on debug entry, check both the T and J bits instead of just the T bit. When the J bit is set, set the right state and warn appropriately. (And while we're at it, move the generic arm struct to the front of the v7a structure, for somewhat better code generation.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: xPSR handling updatesDavid Brownell2009-11-181-17/+20
| | | | | | | | | | When we read the CPSR on debug entry, update the CPSR cache in all cases, not just when the current processor state is User or System. Plus minor cleanup of how the (too-many) other registers' cache entries get updated. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add a default full_context() methodDavid Brownell2009-11-181-9/+3
| | | | | | | | | | | | If the core doesn't provide an optimized version of this method, provide one without core-specific optimizations. Use this to make Cortex-A8 support the "arm reg" command. Related: make the two register access methods properly static, have the "set" log a "not halted" error too, and make sure that the "valid" flag is set on successful reads. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: simplify ARMv7-A register handlingDavid Brownell2009-11-181-33/+45
| | | | | | | | | | | | | | | | | | | ARMv7-A doesn't need to duplicate all the standard ARM code for register handling. - Switch Cortex-A8 to use the standard register code - Remove duplicated infrastructure from ARMv7-A - Have ARMv7-A arch_state() show CPSR, like other ARMs Add comments to show where the Cortex-A8 isn't actually doing the right thing for register reads/writes, unless core happens to be in the right mode to start with. (Looks like maybe there may be generic confusion between saved/current PSR values in all the ARM code ...) Make related ARMv7-A and Cortex-A8 symbols properly static. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add "core_type" field to "struct arm"David Brownell2009-11-181-0/+2
| | | | | | | | | | It's used to flag cores with the "TrustZone" extension, and is used in subsequent patches to set up support for the registers shadowed by its new secure monitor mode. The ARM1176 and Cortex-A8 both support this new mode. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* command_handler: change 'cmd_ctx' to CMD_CTXZachary T Welch2009-11-171-3/+3
| | | | Convert all command handler 'cmd_ctx' parameter usage with CMD_CTX.
* target: remove some more duplicate includesDavid Brownell2009-11-171-1/+0
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: no exit() calls, add missing v7-A initDavid Brownell2009-11-161-31/+16
| | | | | | | Eventually there should be a v7a init routine, but for now all that is inlined here. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: no implicit #includes of "register.h"David Brownell2009-11-161-2/+1
| | | | | | | | | | | | Same deal: "register.h" got needlessly included all over the place because of being in a few widely included headers. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Also, don't need that extra "types.h" inclusion. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: don't implicitly include "breakpoint.h"David Brownell2009-11-161-0/+1
| | | | | | | | | | | Most files in the tree seem to have ended up including this, and *quite* needlessly ... only code implementing or using breakpoints actually needs these declarations. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: memory utils aren't ARM7/ARM9 dependentDavid Brownell2009-11-151-2/+3
| | | | | | | | | | | | | | | | The arm7_9_checksum_memory() and arm7_9_blank_check_memory() routines are not actually specific to the ARM7 and ARM9 core generations ... they can work for any core which can run algorithms using basic ARM (not Thumb) instructions. Rename them; move the declarations to a more generic site; likewise move the code (and tidy it a bit in the process). NOTE: the blank_check() method falsely returned a success status (0) on one error path, when the algorithm failed. Fixed this bug. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: make "examined" flag be per-targetDavid Brownell2009-11-151-3/+3
| | | | | | | | | | | | | | | | | | Previously this flag was stored in "target_type", so that for example if there were two ARM7TDMI targets in a scan chain, both would claim to have been examined although only the first one actually had its examine() method called. Move this state to where it should have been in the first place, and hide a method that didn't need exposure ... the flag is write-once. Provide some doxygen. The examine() method is confusing, since it isn't separating one-time setup from the after-each-reset stuff. And the ARM7/ARM9 version is, somewhat undesirably, not leaving the debug state alone after reset ... probably more of an issue for trace setup than for watchpoints and breakpoints. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* command_t -> struct commandZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct command.
* command_context_t -> struct command_contextZachary T Welch2009-11-131-2/+2
| | | | Remove misleading typedef and redundant suffix from struct command_context.
* target_t -> struct targetZachary T Welch2009-11-131-47/+47
| | | | Remove misleading typedef and redundant suffix from struct target.
* target_type_t -> struct target_typeZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct target_type.
* armv4_5_common_t -> struct armZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and just use struct arm.
* cortex_a8_wrp_t -> struct cortex_a8_wrpZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct cortex_a8_wrp.
* cortex_a8_brp_t -> struct cortex_a8_brpZachary T Welch2009-11-131-3/+3
| | | | Remove misleading typedef and redundant suffix from struct cortex_a8_brp.
* breakpoint_t -> struct breakpointZachary T Welch2009-11-131-9/+9
| | | | Remove misleading typedef and redundant suffix from struct breakpoint.
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