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* CortexA8: Implement debug base autodetectionMarek Vasut2010-11-051-7/+12
| | | | | | | Implement autodetection of debug base. Also, implement a function solving various hardware quirks (like iMX51 ROM Table location bug). Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* propagate return status of set_breakpoint() up call chainMike Dunn2010-09-131-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Hi everyone, I figured since I was poking around in the breakpoint code on other arches, I'd add this change to those arches that don't do it already. This patch propagates the return code of <arch>_set_breakpoint() up the call stack. This ensures that the higher layer breakpoint infrastructure is aware that an error ocurred, in which case the breakpoint is not recorded. Normally I wouldn't touch code that I can't test, but the code is very uniform across architectures, and the change is rather benign, so I figured after careful inspection that it is safe. If the maintainers or others think this is imprudent, the patch can be dropped. Also changed the error code to something more appropriate in two cases where hardware resources are unavailable. Comments and criticisms of course gratefully received. Mike Signed-off-by: Mike Dunn <mikedunn@newsguy.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* debug: debug entry error propagationØyvind Harboe2010-07-191-3/+11
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: added timeout handlingØyvind Harboe2010-07-191-5/+28
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm: add error propagation for enable/disable mmu cachesØyvind Harboe2010-07-191-10/+16
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm: add error propagation to generic get_ttb fnØyvind Harboe2010-07-191-4/+13
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: lots of error propagation fixesØyvind Harboe2010-07-191-18/+53
| | | | | | found by code inspection Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: mem_ap_read_buf_u32() error handlingØyvind Harboe2010-07-191-1/+3
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: add missing error handling for ↵Øyvind Harboe2010-07-191-3/+9
| | | | | | cortex_a8_dap_write/read_coreregister_u32() Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: add missing error handling from cortex_a8_exec_opcode()Øyvind Harboe2010-07-191-13/+52
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: add missing error handling for mem_ap_atomic_write_u32()Øyvind Harboe2010-07-191-1/+5
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: add missing error handling for mem_ap_read_atomic_u32()Øyvind Harboe2010-07-191-0/+11
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* spelling fixes in commentsØyvind Harboe2010-07-181-5/+5
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: only physical read/write's are available when target is runningØyvind Harboe2010-06-221-2/+9
| | | | | | | | | Memory read/writes to virtual memory, requires that the CPU is halted. Use 'phys' option to write to memory while target is running. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: print message that locking debug access succeeded on second tryØyvind Harboe2010-06-221-0/+4
| | | | | | | when locking the debug access fails on the first try, it's a bit noisy, so print out message that it succeeded on second try. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: add error propagation for poll/resumeØyvind Harboe2010-06-221-5/+15
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: add timeouts waiting for restart, prepare and haltØyvind Harboe2010-06-221-6/+36
| | | | | | | It would previously sit in an infinite loop rather than reporting an error. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: add error propagation for mem_ap_read/write_atomic_u32Øyvind Harboe2010-06-221-7/+31
| | | | | | | Error propagation avoids e.g. infinite loops waiting for target to halt, etc. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: add missing error handlingØyvind Harboe2010-06-211-3/+11
| | | | | | cortex examine was missing error handling. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a8: fix segfault for unexamined targetsØyvind Harboe2010-06-191-3/+6
| | | | | | | print error message instead of segfaulting for unexamined targets. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex_a8: -Wshadow warning fixesØyvind Harboe2010-06-151-9/+9
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* TARGET: removed unused parametersAntonio Borneo2010-06-121-3/+1
| | | | | | | Parameters "domain" and "ap" of function armv4_5_mmu_translate_va() are not used. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
* TARGET: removed unsed parameterAntonio Borneo2010-06-121-2/+1
| | | | | | | | Parameter "type" of function armv4_5_mmu_translate_va() is now not used. Remove the parameter and the "enum" listing its values. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
* TARGET: fix handling return code of MMU translationAntonio Borneo2010-06-121-4/+0
| | | | | | | | | Function armv4_5_mmu_translate_va() now properly signals errors in the return value. Remove former error handling by setting variable "type" to value "-1". Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
* arm mmu: error propagation added for address translationØyvind Harboe2010-06-111-2/+5
| | | | | | | The return value for MMU translation was a mess, either error or value. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex-a8: more MMU supportAnton Fedotov2010-04-141-98/+318
| | | | | | | | | | | | | | | | | | | + virt2phys() can now convert virtual address to real + read_memory() and write_memory() are renamed to read_phys_memory() and write_phys_memory() + new read_memory() and write_memory() try to resolve real address if mmu is enambled than perform real address reading/writing + if address is bellow 0xc000000 than TTB0 is used for page table dereference, if above - than TTB1. Linux style of user/kernel address separation + if above fails (i.e address is unspecified) than mode is checked whether it is Supervisor (than TTB1) or User (than TTB0) - Software breakpoints doesn't work. You should invoke "gdb_breakpoint_override hard" before you start debugging + cortex_a8_mmu(), cortex_a8_enable_mmu_caches(), cortex_a8_disable_mmu_caches() are implemented Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm7/9: remove unused post_restore_contextØyvind Harboe2010-03-171-4/+0
| | | | | | | Unused. If something should happen after context restore, then the calling code can just do it afterwards. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ADIv5 share DAP command supportDavid Brownell2010-03-051-21/+23
| | | | | | | | | | | | | | Get rid of needless and undesirable code duplication for all the DAP commands (resolving a FIXME) ... there's no need for coreas to have private copies of that stuff. Stick a pointer to the DAP in "struct arm", letting common code get to it. Also rename the "swjdp_info" symbol; just call it "dap". This is an overall code shrink. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* rename "swjdp_common" as "adiv5_dap"David Brownell2010-03-041-18/+18
| | | | | | | | | | | | | This partially corrects an inappropriate name choice (and its associated FIXME). There are still too many variables named "swjdp", bug little current code actually relies on them referencing an SWJ-DP instead of some other flavor of DAP. Only the two new dap_to{swd,jtag}() calls could behave differently on an SWJ-DP instead of a SW-DP or a JTAG-DP. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5 clean up AP selection and register cachingDavid Brownell2010-02-211-4/+4
| | | | | | | | | | | | | | | | | | | Handling of AP (and AP register bank) selection, and cached AP registers, is pretty loose ... start tightening it: - It's "AP bank" select support ... there are no DP banks. Rename. + dap_dp_bankselect() becomes dap_ap_bankselect() + "dp_select_value" struct field becomes "ap_bank_value" - Remove duplicate AP cache init paths ... only use dap_ap_select(), and don't make Cortex (A8 or M3) cores roll their own code. - For dap_ap_bankselect(), pass up any fault code from writing the SELECT register. (Nothing yet checks those codes.) - Add various bits of Doxygen Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: keep a handle to the PCDavid Brownell2010-02-211-9/+6
| | | | | | | | | | | | | | | | Keep a handle to the PC in "struct arm", and use it. This register is used a fair amount, so this is a net minor code shrink (other than some line length fixes), but mostly it's to make things more readable. For XScale, fix a dodgy sequence while stepping. It was initializing a variable to a non-NULL value, then updating it to handle the step-over-active-breakpoint case, and then later testing for non-NULL to see if it should reverse that step-over-active logic. It should have done like ARM7/ARM9 does: init to NULL. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: debug messaging tweaksDavid Brownell2010-01-271-5/+6
| | | | | | | Make that "TODO" message say what needs to be done. Say what part of examining failed. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7: help/usage updatesDavid Brownell2010-01-071-2/+2
| | | | | | | | | | | | | | | | | | Provide helptext which was sometimes missing; update some of it to be more accurate. Usage syntax messages have the same EBNF as the User's Guide; there should be no angle brackets in either place. Don't use "&function"; functions are like arrays, their address is their name. Shrink some overlong lines, remove some empties. Add a couple comments about things that should change: those extra TCK cycles for MEM-AP reads are in the wrong place (that might explain some problems we've seen); the DAP command tables should be shared, not copied. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add comment re register exportsDavid Brownell2009-12-261-0/+1
| | | | Modern versions of GDB can understand VFP3 and iwMMXt hardware.
* ARM: rename some generic routinesDavid Brownell2009-12-071-2/+2
| | | | | | | | | | | | | | | | Rename some (mostly) generic ARM functions: armv4_5_arch_state() --> arm_arch_state() armv4_5_get_gdb_reg_list() --> arm_get_gdb_reg_list() armv4_5_init_arch_info() --> arm_init_arch_info() Cores using the microcontroller profile may want a different arch_state() routine though. (Also fix strange indentation in arm_arch_state: use tabs only! And update a call to it, removing assignment-in-conditional.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: move opcode macros to <target/arm_opcodes.h>David Brownell2009-12-071-0/+1
| | | | | | | | | | | | | | | Move the ARM opcode macros from <target/armv4_5.h>, and a few Thumb2 ones from <target/armv7m.h>, to more appropriate homes in a new <target/arm_opcodes.h> file. Removed duplicate opcodes from that v7m/Thumb2 set. Protected a few macro argument references by adding missing parentheses. Tightening up some of the line lengths turned up a curious artifact: the macros for the Thumb opcodes are all 32 bits wide, not 16 bits. There's currently no explanation for why it's done that way... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename ARMV4_5_STATE_* as ARM_STATE_*David Brownell2009-12-041-4/+4
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM DPM: share debug reason logicDavid Brownell2009-12-031-25/+12
| | | | | | | | | | | | | | | | | | No point in both ARM11 and Cortex-A8 having private copies of the logic sorting out e.g. DBG_REASON_WATCHPOINT. Add and use a shared routine for this ... there's actually a bunch more debug entry logic that could be shared, this is just a start on that. Note that this routine fixes a bug observed in the ARM11 code, where some abort mode quirks were displayed as being an unknown debug reason; and also silences needless ARM11 chatter. Likewise with private copies of DSCR ... add one to the DPM struct. Save it as part of setting DBG_REASON_* so later patches can switch over to using that copy. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM DPM: make DSCR bit defs sharableDavid Brownell2009-12-031-23/+29
| | | | | | | | | | | | | | | | Move the symbols for these bits from "armv7a.h" to "arm_dpm.h", where they can be seen and used not just by Cortex-A but also by the ARM11 (armv6) code. Change them from bit numbers to bit masks ... this matches the usage in ARM11 code, and also makes it easier to read. Rename DSCR_EXT_INT_EN as DSCR_ITR_EN to match the docs; it's enabling ITR functionality, not external interrupts, so this changes the name to be less misleading. (There *IS* a bit affecting interrupts, and this isn't it.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM DPM: tweak initializationDavid Brownell2009-12-021-1/+6
| | | | | | Move the initial breakpoint/watchpoint disable calls to arm_dpm_initialize(), and start using that routine. This split helps with arm11 support.
* ARMv7a/Cortex-A8: report watchpoint trigger insnDavid Brownell2009-12-021-22/+8
| | | | | | | | | | | Save and display the address of the instruction which triggered the watchpoint. Because of pipelining, that's well behind the PC value when debug entry completes. (Example in a subroutine that had been returned from...) Remove unused A8 stuff, mostly watchpoint hooks from the header. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: basic watchpoint supportDavid Brownell2009-12-011-0/+66
| | | | | | | Actually this should handle both breakpoints and watchpoints ... but the DPM framework only handles watchpoints for now. Works on Beagle. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: core DPM support for watchpointsDavid Brownell2009-12-011-8/+4
| | | | | | | | | | | | | | | | | | | | | This is a NOP unless the underlying core exposes two new methods, and neither of the two cores using this (ARM11xx, Cortex-A8) do so yet. This patch only updates those cores so they pass a flag saying whether or not to update breakpoint and watchpoint status before resuming; and removing some now-needless anti-segfault code from ARM11. Cortex-A8 didn't have that code ... yes, it segfaulted when setting watchpoints. NOTE: this uses a slightly different strategy for setting/clearing breakpoints than the ARM7/ARM9/etc code uses. It leaves them alone unless it's *got* to change something, to speed halt/resume cycles (including single stepping). ALSO NOTE: this under-delivers for Cortex-A8, where regions with size up to 2 GBytes can be watched ... it handles watchpoints which ARM11 can also handle (size 1/2/4 bytes). Should get fixed later. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: remove previous mcr()/mrc() methodsDavid Brownell2009-12-011-97/+1
| | | | | | | | We don't need this code, now that the DPM code handles it. Neither do we need the ARMv7-A CP15 operations; remove their remnants too. And disable a mostly-needless diagnostic. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: "mcr" and "mrc" are ARM-specificDavid Brownell2009-12-011-5/+6
| | | | | | | | | | | | | | Switch "mrc" and "mcr" commands to be toplevel ARM operations, as they should initially have been. Correct the usage message for both commands: it matches ARM documentation (as one wants!) instead of reordering them to match the funky mrc() and mcr() method usage (sigh). For Cortex-A8: restore a line that got accidentally dropped, so the secure monitor mode shadow registers will show again. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: stop using CP15 opsDavid Brownell2009-12-011-16/+53
| | | | | | | | | | | | | | | | | | | | | There were two chunks of Cortex-A8 code which called the ARMv7-A CP15 operations; get rid of them, helping prepare to remove those methods completely: - post_debug_entry() can use the mrc() method to read its two registers. - write_memory() can use dpm->instr_write_data_r0() to flush the ICache and DCache ... doing it this way is actually faster since it reduces per-write overhead. Note that the mrc() method parameters are re-ordered with respect to the ARM instruction documentation, so that part can be confusing. Cleaned up the layout and comments in those areas a bit. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: support "reset-assert" eventDavid Brownell2009-11-271-5/+28
| | | | | | | | | | | | | | Use the new "reset-assert" event; else SRST; else fail. Tested on an OMAP3, using the event. NOTE: still doesn't handle "reset halt". For some reason neither VCR nor PRCR seemed effective; they held the value that was written, but VCR didn't trigger debug entry when the reset vector fired (maybe the vector needs configuring?) and PRCR refused to hold the chip in reset until deassert() could force the core into debug state. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* remove target_type register_command callbackZachary T Welch2009-11-241-8/+7
| | | | | | Uses chaining of command_registration structures to eliminate all target_type register_callback routines. Exports the command_handler registration arrays for those target types that are used by others.
* cortex_a8: use register_commands()Zachary T Welch2009-11-241-17/+25
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* use COMMAND_REGISTER macroZachary T Welch2009-11-241-3/+3
| | | | | Replaces direct calls to register_command() with a macro, to allow its parameters to be changed and callers updated in phases.
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