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* simplify and unconfuse target_run_algorithm()David Brownell2010-04-042-19/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | For some reason there are *two* schemes for interposing logic into the run_algorithm() code path... One is a standard procedural wapper around the target method invocation. the other (superfluous) one hacked the method table by splicing a second procedural wrapper into the method table. Remove it: * Rename its slightly-more-featureful wrapper so it becomes the standard procedural wrapper, leaving its added logic (where it should have been in the first place. Also add a paranoia check, to report targets that don't support algorithms without traversing a NULL pointer, and tweak its code structure a bit so it's easier to modify. * Get rid of the superfluous/conusing method table hacks. This is a net simplification, making it simpler to analyse what's going on, and then interpose logic . ... by ensuring there's only one natural place for it to live. ------------ Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* xscale: fix trace buffer functionality when resuming from a breakpointMike Dunn2010-03-291-9/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Problem: halt at a breakpoint, enable trace buffer ('xscale trace_buffer enable fill'), then resume. Wait for debug exception when trace buffer fills (if not sooner due to another breakpoint, vector catch, etc). Instead, never halts. When halted explicitly from OpenOCD and trace buffer dumped, it contains only one entry; a branch to the address of the original breakpoint. If the above steps are repeated, except that the breakpoint is removed before resuming, the trace buffer fills and the debug exception is generated, as expected. Cause: related to how a breakpoint is stepped over on resume. The breakpoint is temporarily removed, and a hardware breakpoint is set on the next instruction that will execute. xscale_debug_entry() is called when that breakpoint hits. This function checks if the trace buffer is enabled, and if so reads the trace buffer from the target and then disables the trace (unless multiple trace buffers are specified by the user when trace is enabled). Thus you only trace one instruction before it is disabled. Solution: kind of a hack on top of a hack, but it's simple. Anything better would involve some refactoring. This has been tested and trace now works as intended, except that the very first instruction is not part of the trace when resuming from a breakpoint. TODO: still many issues with trace: doesn't work during single-stepping (trace buffer is flushed each step), 'xscale analyze_trace' works only marginally for a trace captured in 'fill' mode, and not at all for a trace captured in 'wrap' mode. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* target: fix poll offØyvind Harboe2010-03-251-0/+6
| | | | | | | | | | | I don't know when "poll off" broke, but "poll off" didn't stop background polling of target. The polling status flag simply wasn't checked in the handle_target timer callback. All target polling(including power/reset state) is now stopped upon "poll off". Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* change %x and %d to PRIx32 and PRId32 where needed for cygwinDaniel Bäder2010-03-252-2/+2
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* fix software breakpoints on xscaleMike Dunn2010-03-221-2/+12
| | | | | | | | | | | | | | | | | | | | | | This patch fixes xscale software breakpoints by cleaning the dcache and invalidating the icache after the bkpt instruction is inserted or removed. The icache operation is necessary in order to flush the fetch buffers, even if the icache is disabled (see section 4.2.7 of the xscale core developer's manual). The dcache is presumed to be enabled; no harm done if not. The dcache is also invalidated after cleaning in order to safeguard against a future load of invalid data, in the event that cache_clean_address points to memory that is valid and in use. Also corrected a confusing typo I noticed in a comment. TODO (or not TODO...?): the xscale's 2K "mini dcache" is not cleaned. This cache is not used unless the 'X' bit in the page table entry is set. This is a proprietary xscale extension to the ARM architecture. If a target's OS or executive makes use of this for memory regions holding code, the breakpoint problem will persist. Flushing the mini dcache requires that 2K of valid cacheable memory (mapped with 'X' bit set) be designated by the user for this purpose. The debug handler that gets downloaded to the target will also need to be extended.
* arm breakpoints: amended fix commentØyvind Harboe2010-03-212-2/+11
| | | | | | | | the handling of caches, should be moved into the breakpoint specific callbacks rather than being plonked into generic memory write fn's. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* jtag: make out_value constØyvind Harboe2010-03-213-57/+54
| | | | | | Tightens up the jtag_add_xxx_scan() API Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* jtag: move towards making out_value constØyvind Harboe2010-03-203-5/+5
| | | | | | | These were relatively straightforward fixes which are backwards compatible. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* jtag: retire jtag_get/set_end_state()Øyvind Harboe2010-03-1915-58/+0
| | | | | | | Voila! This get rids of mysteries about what what state the TAP is in. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* jtag: remove jtag_get_end_state() usageØyvind Harboe2010-03-191-4/+4
| | | | | | | Code inspection indicated what constant end states to use. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* jtag: get rid of unecessary jtag_get_end_state()Øyvind Harboe2010-03-191-12/+21
| | | | | | By code inspection. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* jtag: remove unecessary usage of jtag_get_end_state().Øyvind Harboe2010-03-191-2/+2
| | | | | | By code inspection. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* jtag: remove jtag_get_end_state()'s that should be unecessaryØyvind Harboe2010-03-194-5/+5
| | | | | | | | By a bit of code inspection it seems like all of these instances of jtag_get_end_state() can be unambigously replaced by constants. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* Fix underlying problem with xscale icache and dcache commandsMike Dunn2010-03-181-6/+11
| | | | | | | | | | | | | | | | | | | | Fix problem with the xscale icache and dcache commands. Both commands were enabling or disabling the mmu, not the caches I didn't look any further after my earlier patch fixed the trivial problem with command argument parsing. Turns out the underlying code was broken. The resolution is straightforward when you look at the arguments to xscale_enable_mmu_caches() and xscale_disable_mmu_caches(). I finally took a deeper look after dumping the cp15 control register (XSCALE_CTRL) and seeing that the cache bits weren't changing, but the mmu bit was (which caused all manner of grief, as you can imagine). This has been tested and works OK now. src/target/xscale.c | 17 +++++++++++------ 1 files changed, 11 insertions(+), 6 deletions(-) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADI_v5 - it's not always an "SWJ-DP"David Brownell2010-03-182-175/+175
| | | | | | | So don't use the name "swjdp" for all DAPs; rename to plain old "dap", which *is* always correct. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Merge branch 'master' of ↵David Brownell2010-03-1813-73/+74
|\ | | | | | | ssh://dbrownell@openocd.git.sourceforge.net/gitroot/openocd/openocd
| * jtag: retire one instance of jtag_get_end_state() usageØyvind Harboe2010-03-1813-73/+74
| | | | | | | | | | | | Less global variables.... Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* | remove more duplicationDavid Brownell2010-03-181-25/+0
|/ | | | | | | | Not sure how the original "move code to adi_v5_swd.c" patch left some code in the "arm_adi_v5.c" file, but a recent patch was only a partial fix -- it didn't remove all the duplication. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* oops: committed and pushed two temp files....Øyvind Harboe2010-03-182-3962/+0
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* PIC32MX: add unlock cmdSpencer Oliver2010-03-181-0/+2
| | | | | | | 'unlock' performs a full unlock/erase of the device, removing any code protection. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* MIPS: remove unused arg from mips_ejtag_set_instrSpencer Oliver2010-03-185-51/+51
| | | | | | This arg was never used and was just taken from the arm jtag code. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* jtag: cut down on usage of unintended modification of global end stateØyvind Harboe2010-03-1819-72/+4031
| | | | | | | | | | | | | jtag_get/set_end_state() is now deprecated. There were lots of places in the code where the end state was unintentionally modified. The big Q is whether there were any places where the intention was to modify the end state. 0.5 is a long way off, so we'll get a fair amount of testing. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* linker error: fix problem with duplicate fnØyvind Harboe2010-03-181-33/+0
| | | | | | | | | | | A fn was copied instead of moved to a new file. The linker can discard exact copies of fn's without warning. This is a C++'ism. However on my Ubuntu 9.10 machine, it fails. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* mips: fix warningØyvind Harboe2010-03-171-1/+1
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* gdb: long running "monitor mww" now works w/gdbØyvind Harboe2010-03-171-0/+2
| | | | | | | invoke keep_alive() to make sure that the default 2000ms timeout does not trigger. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* target: faster mww operationsØyvind Harboe2010-03-171-38/+77
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* target: mdX/mwX on target were badly brokenØyvind Harboe2010-03-171-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - incorrect parsing of arguments - mdX didn't display arguments correctly I don't think anyone ever used that code path :-) Did you know that "target mdw" and mdw are very different? for {set i 0} {$i < 256} {set i [expr $i+1]} {mwb [expr 0x2000000+$i] $i} mdw 0x2000000 0x10 0x02000000: 03020100 07060504 0b0a0908 0f0e0d0c 13121110 17161514 1b1a1918 1f1e1d1c 0x02000020: 23222120 27262524 2b2a2928 2f2e2d2c 33323130 37363534 3b3a3938 3f3e3d3c > zy1000.cpu mdb 0x2000000 0x20 0x02000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f ................ 0x02000010 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f ................ > zy1000.cpu mdh 0x2000000 0x20 0x02000000 0100 0302 0504 0706 0908 0b0a 0d0c 0f0e ................ 0x02000010 1110 1312 1514 1716 1918 1b1a 1d1c 1f1e ................ 0x02000020 2120 2322 2524 2726 2928 2b2a 2d2c 2f2e !"#$%&'()*+,-./ 0x02000030 3130 3332 3534 3736 3938 3b3a 3d3c 3f3e 0123456789:;<=>? > zy1000.cpu mdw 0x2000000 0x20 0x02000000 03020100 07060504 0b0a0908 0f0e0d0c ................ 0x02000010 13121110 17161514 1b1a1918 1f1e1d1c ................ 0x02000020 23222120 27262524 2b2a2928 2f2e2d2c !"#$%&'()*+,-./ 0x02000030 33323130 37363534 3b3a3938 3f3e3d3c 0123456789:;<=>? 0x02000040 43424140 47464544 4b4a4948 4f4e4d4c @ABCDEFGHIJKLMNO 0x02000050 53525150 57565554 5b5a5958 5f5e5d5c PQRSTUVWXYZ[\]^_ 0x02000060 63626160 67666564 6b6a6968 6f6e6d6c `abcdefghijklmno 0x02000070 73727170 77767574 7b7a7978 7f7e7d7c pqrstuvwxyz{|}~. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* PIC32: add software reset supportSpencer Oliver2010-03-174-3/+61
| | | | | | | | | The PIC32MX does not support the ejtag software reset - it is optional in the ejtag spec. We perform the equivalent using the microchip specific MTAP cmd's. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* MIPS: remove ejtag_srst variantSpencer Oliver2010-03-172-17/+17
| | | | | | | | | | | The mips_m4k_assert_reset has now been restructured so the variant ejtag_srst is not required anymore. The ejtag software reset will be used if the target does not have srst connected. Remove ejtag_srst from docs. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* arm7/9: remove unused post_restore_contextØyvind Harboe2010-03-1710-20/+0
| | | | | | | Unused. If something should happen after context restore, then the calling code can just do it afterwards. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ADIv5 transport support moves to separate filesDavid Brownell2010-03-165-430/+589
| | | | | | | | | | | | | | | | | | | Unclutter arm_adi_v5.c by moving most transport-specific code to a transport-specific files adi_v5_{jtag,swd}.c ... it's not a full cleanup, because of some issues which need to be addressed as part of SWD support (along with implementing the DAP operations on top of SWD transport): - The mess where mem_ap_read_buf_u32() is currently coded to know about JTAG scan chains, and thus needs rewriting before it will work with SWD; - Initialization is still JTAG-specific Also move JTAG_{DP,ACK}_* constants from adi_v5.h to the JTAG file; no other code should care about those values. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* image loading: fix problem with offsets > 0x80000000Bradey Honsinger2010-03-163-3/+3
| | | | | | | | | | | | | | | Fixes bug that prevented users from specifying a base address of 0x80000000 or higher in image commands (flash write_image, etm image, xscale trace_image). image.base_address is an offset from the start address contained in the image file (if there is one), or from 0 (for binary files). As a signed 32-bit int, it couldn't be greater than 0x7fffffff, which is a problem when trying to write a binary file to flash above that address. Changing it to a 64-bit long long keeps it as a signed offset, but allows it to cover the entire 32-bit address space. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* fix xscale icache and dcache commandsMike Dunn2010-03-111-3/+3
| | | | | | | | | Simple patch that fixes the broken xscale icache and dcache commands. This broke when the helper functions and macros were changed. [ dbrownell@users.sourceforge.net: don't use strcasecmp ] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* MIPS: make fixed code arrays static constSpencer Oliver2010-03-101-3/+3
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* PIC32: add flash algorithm supportSpencer Oliver2010-03-103-3/+7
| | | | | | | | | | | | | Add flash algorithm support for the PIC32MX. Still a few things todo but this dramatically decreases the programing time, eg. approx programming for 2.5k test file. - without fastload: 60secs - with fastload: 45secs - with fastload and algorithm: 2secs. Add new devices to supported list. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* jtag: simplify jtag_add_plain_ir/dr_scanØyvind Harboe2010-03-082-24/+5
| | | | | | | These fn's now clearly just clock out/in bits. No mystical fields are involved. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* jtag: jtag_add_ir_scan() now takes a single fieldØyvind Harboe2010-03-085-8/+8
| | | | | | | | In the code a single field was all that was ever used. Makes jtag_add_ir_scan() simpler and leaves more complicated stuff to jtag_add_plain_ir_scan(). Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* jtag: retire tap fieldØyvind Harboe2010-03-0819-198/+81
| | | | | | | | | | | | | | | | | jtag_add_dr/ir_scan() now takes the tap as the first argument, rather than for each of the fields passed in. The code never exercised the path where there was more than one tap being scanned, who knows if it even worked. This simplifies the implementation and reduces clutter in the calling code. use jtag_add_ir/dr_plain_scan() for more fancy situations. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ADIv5 share DAP command supportDavid Brownell2010-03-059-335/+174
| | | | | | | | | | | | | | Get rid of needless and undesirable code duplication for all the DAP commands (resolving a FIXME) ... there's no need for coreas to have private copies of that stuff. Stick a pointer to the DAP in "struct arm", letting common code get to it. Also rename the "swjdp_info" symbol; just call it "dap". This is an overall code shrink. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* rename "swjdp_common" as "adiv5_dap"David Brownell2010-03-048-116/+114
| | | | | | | | | | | | | This partially corrects an inappropriate name choice (and its associated FIXME). There are still too many variables named "swjdp", bug little current code actually relies on them referencing an SWJ-DP instead of some other flavor of DAP. Only the two new dap_to{swd,jtag}() calls could behave differently on an SWJ-DP instead of a SW-DP or a JTAG-DP. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* NOR: invalidate cached state on target resumeDavid Brownell2010-03-031-0/+9
| | | | | | | | | | | | | | | | | | | | The NOR infrastructure caches some per-sector state, but it's not used much ... because the cache is not trustworthy. This patch addresses one part of that problem, by ensuring that state cached by NOR drivers gets invalidated once we resume the target -- since targets may then modify sectors. Now if we see sector protection or erase status marked as anything other than "unknown", we should be able to rely on that as being accurate. (That is ... if we assume the drivers initialize and update this state correctly.) Another part of that problem is that the cached state isn't much used (being unreliable, it would have been unsafe). Those issues can be addressed in later patches. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5: use new DAP ops for AP read/writeDavid Brownell2010-03-023-106/+79
| | | | | | | | | | | | | | | | | | | Make ADIv5 internals use the two new transport-neutral calls for reading and writing DP registers; and do the same for external callers. Also, bugfix some of their call sites to handle the fault returns, instead of ignoring them. Remove most of the JTAG-specific calls, using their code as the bodies of the JTAG-specific implementation for the new methods. NOTE that there's a remaining issue: mem_ap_read_buf_u32() makes calls which are JTAG-specific. A later patch will need to remove those, so JTAG-specific operations can be removed from this file, and so that SWD support will be able to properly drop in as just a transport layer to the ADIv5 infrastructure. (The way read results are posted may need some more attention in the transport-neutrality interface.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5: use new DAP ops for DP read/writeDavid Brownell2010-03-021-32/+38
| | | | | | | | | | | Make ADIv5 internals use the two new transport-neutral calls for reading and writing DP registers. Also, bugfix some of their call sites to handle the fault returns, instead of ignoring them. Remove the old JTAG-specific calls, using their code as the bodies of the JTAG-specific implementation for the new methods. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5: use new dap_run() operationDavid Brownell2010-03-023-37/+74
| | | | | | | | | | Make ADIv5 use one of the new transport-neutral interfaces: call dap_run(), not jtagdp_transaction_endcheck(). Also, make that old interface private; and bugfix some of its call sites to handle the fault returns, instead of ignoring them. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: start abstracting ADIv5 transports (JTAG/SWD)David Brownell2010-03-022-0/+278
| | | | | | | | | | | | | | | | | | | | | | | | | | | | To support both JTAG and SWD, ADIv5 needs DAP operations which are transport-neutral, instead being of JTAG-specific. This patch: - Defines such a transport-neutral interface, abstracting access to DP and AP registers through a conceptual queue of operations. - Builds the first implementation of such a transport with the existing JTAG-specific code. In contrast to the current JTAG-only interface, the interface adds support for two previously-missing (and unused) DAP operations: - aborting the current AP transaction (untested); - reading the IDCODE register (tested) ... required for SWD init. The choice of transports may be fixed at the chip, board, or JTAG/SWD adapter level. Or if all the relevant hardware supports both transport options, the choice may be made at runtime, This patch provides basic infrastructure to support whichever choice is made. The current "JTAG-only" transport choice policy will necessarily continue for now, until SWD support becomes available in OpenOCD. Later patches start phasing out JTAG-specific calls in favor of transport-neutral calls. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target_resume() doxygenDavid Brownell2010-03-021-3/+33
| | | | | | | | | | | Add doxygen for target_resume() ... referencing the still-unresolved confusion about what the "debug_execution" parameter means (not all CPU support code acts the same). The 'handle_breakpoints" param seems to have resolved the main issue with its semantics, but it wasn't part of the function spec before. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ADIv5: use right ID for Cortex-M3 ETMDavid Brownell2010-03-021-4/+4
| | | | | | | | | Correct a mistake made copying the ID of the Cortex-M3 ETM module from the TRM, so that "dap info" on a CM3 with an ETM will now correctly describe ROM table entries for such modules. (They are included on LPC17xx and some other cores.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* arm_semihosting buildfixDavid Brownell2010-03-011-8/+14
| | | | | | | | | | | | | | The recent "add armv7m semihosting support" patch introduced two build errors: arm_semihosting.c: In function ‘do_semihosting’: arm_semihosting.c:71: error: ‘spsr’ may be used uninitialized in this function arm_semihosting.c:71: error: ‘lr’ may be used uninitialized in this function This fixes those build errors. The behavior is, however, untested. (Also, note the two new REVISIT comments.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* armv4_5: remove core_type check in mcr/mrc cmdSpencer Oliver2010-02-281-7/+0
| | | | | | | core_type check is not required as the core function will be null for cores that do not support the mcr/mrc functions. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* semihosting: add armv7m semihosting supportSpencer Oliver2010-02-283-76/+137
| | | | | | | do_semihosting and arm_semihosting now check the core type and use the generic arm structure. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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