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* mips: add nor flash write from memory blockStefan Mahr2011-06-051-1/+5
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* crc check on flashed dataRodrigo L. Rosa2011-06-041-10/+71
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* code cleanupRodrigo L. Rosa2011-06-041-21/+11
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* Fix "unused variable" warnings (errors) detected with GCC 4.7.0 - dubious fixesFreddie Chopin2011-06-041-4/+0
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* Fix "unused variable" warnings (errors) detected with GCC 4.7.0 - trivial fixesFreddie Chopin2011-06-0413-60/+10
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* mips: fixup fastdataStefan Mahr2011-06-012-6/+10
| | | | fixup fastdata
* mips: fix some more endian madnessStefan Mahr2011-06-012-63/+59
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* mips: fix swapping if running on big endian hostStefan Mahr2011-05-291-3/+19
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* mips: fix swapping if openocd is running on big endian hostStefan Mahr2011-05-281-1/+4
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* dsp5680xx: whitespace cleanupSpencer Oliver2011-05-231-43/+43
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* Fix build issue under cygwinSpencer Oliver2011-05-231-1/+1
| | | | | | | cygwin does not define sleep, so use our internal win32 version. caused by commit 9d4aec6bda90ad39a140747ea270c6a09dd26440 Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* flashing speed improved using queued jtag. error propagation improved.Rodrigo L. Rosa2011-05-192-287/+351
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* partial support for 568013 and 568037, target integration.Rodrigo L. Rosa2011-05-184-1/+1572
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* Remove useless MIPS code in avr32_ap7k.c.Jie Zhang2011-05-031-4/+0
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* cortex_a : smp supportMichel Jaouen2011-04-281-15/+230
| | | | | | Conflicts: src/target/cortex_a.c
* smp : infra for smp minimum supportMichel Jaouen2011-04-286-15/+335
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* RTOS Thread awareness support wipBroadcom Corporation (Evan Hunter)2011-04-152-0/+27
| | | | | | | | | | | - works on Cortex-M3 with ThreadX and FreeRTOS Compared to original patch a few nits were fixed: - remove stricmp usage - unsigned compare fix - printf formatting fixes - fixed a bug with overrunning a memory buffer allocated with malloc.
* Replace byte-access to memory with faster word-accessLuca Ellero2011-04-131-21/+69
| | | | | | | | | Freescale iMX53 doesn't seem to like unaligned accesses to his memory mapped registers. Anyway this patch makes dump_image/load_image 4X faster for every access through APB. Signed-off-by: Luca Ellero <lroluk@gmail.com>
* Add opcodes for load/store registers words immediate post-indexedLuca Ellero2011-04-131-0/+12
| | | | Signed-off-by: Luca Ellero <lroluk@gmail.com>
* cortex_a :apb mem read/write working with mmu_onMichel JAOUEN2011-04-131-159/+171
| | | | | | Conflicts: src/target/cortex_a.c
* cortex_a : multiple target on the same dapMichel JAOUEN2011-04-131-0/+10
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* cortex_a : use dap ref from armv4_5commonMichel JAOUEN2011-04-131-18/+18
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* cortex_a : implement jtag console for cortex_aMichel JAOUEN2011-04-061-46/+13
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* Added mips_ejtag_drscan_32_out() for optimization.Drasko DRASKOVIC2011-04-054-6/+22
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* Corrected waiting on PrAcc in wait_for_pracc_rw(). Added necessary check ↵Drasko DRASKOVIC2011-04-051-14/+42
| | | | that PrAcc is "1" before FASTDATA access.
* Added correct endianess treatment for big endian targets. Now it is possible ↵Drasko DRASKOVIC2011-04-051-6/+72
| | | | to use mips_m4k_write_memory() and mips_m4k_read_memory() to correctly set-up SDRAM, as well as bulk data write, which already handled endianess well. Also added correct endianess manipulation in case of fallback from erroneus bulk write to simple write (to avoid byte swapping two times).
* cortex_a: delete dbgbase hack vestigesØyvind Harboe2011-04-011-15/+0
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex_a: fix gaffe in first implementation of -dbgbaseMichel JAOUEN2011-04-011-9/+9
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* Merge remote branch 'origin/master' into HEADØyvind Harboe2011-04-0130-159/+152
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| * cortex_a: remove broken dbgbase patchup codeØyvind Harboe2011-04-011-25/+0
| | | | | | | | | | | | | | | | | | | | the patchup code would get false positives when checking whether a dbgbase had to be corrected. The solution is to have autodetect default, with manual override in scripts. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
| * mips: illustrates how to improve performanceØyvind Harboe2011-04-013-8/+18
| | | | | | | | | | | | | | Do not require unecessary roundtrips for clocking out data. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
| * types: write memory now uses constØyvind Harboe2011-04-0127-80/+80
| | | | | | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
| * mips: delete kludgy code that modifies data sent to write_memory()Øyvind Harboe2011-03-311-1/+16
| | | | | | | | | | | | | | | | Could this cause confusion as data sent to write would be flipped and then if the caller subsequently used the data, e.g. a compare mismatch might happen? Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
| * mips: mips32_pracc_exec error propagation fixesØyvind Harboe2011-03-312-29/+21
| | | | | | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
| * mips: mips_ejtag_get_impcode error propagation addedØyvind Harboe2011-03-312-2/+7
| | | | | | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
| * mips: fix mips_ejtag_set_instr error handlingØyvind Harboe2011-03-312-14/+10
| | | | | | | | | | | | this fn does not fail, it queues data. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* | mips: fix gaffe in previous commitØyvind Harboe2011-04-011-1/+4
|/ | | | | | | | accidentally invoked return jtag_execute_queue() in the middle of a fn. Hmm.... I would have expected gcc or at least lint to catch this. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* mips: fix error handling for jtag_execute_queue()Øyvind Harboe2011-03-312-8/+8
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* xscale: fix gaffe in phys writeØyvind Harboe2011-03-311-1/+1
| | | | | | | it would *read* instead of *write* to memory when the MMU was disabled. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex-a: use -dbgbase optionØyvind Harboe2011-03-311-5/+12
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* target: add -dbgbase option to target configurationØyvind Harboe2011-03-312-0/+23
| | | | | | | | | Really a Cortex-A specific option, but there is no system in place to support target specific options currently and there has been no need for such a system until now. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* bugfix for step <address> mips_m4kAndrew Lyon2011-03-291-0/+4
| | | | | | | | | The patch below fixes step <address> on mips_m4k. Spencer Oliver <spen@spen-soft.co.uk>: The current code is used on all other arch's - is there a underlying issue with those aswell ?
* cortex_a: rename cortex_a8.c/h to cortex_a.c/hØyvind Harboe2011-03-223-3/+3
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* omap4430: tried to add in workaround for broken dbgbase queryØyvind Harboe2011-03-221-0/+1
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cortex a9: merge cortex a9 and a8 codeØyvind Harboe2011-03-226-2512/+289
| | | | | | better to keep this in a single file. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* dsp563xx_once: fix warning and potential bugØyvind Harboe2011-03-201-1/+1
| | | | | | | | I don't think dsp563xx_once_read_register() would ever be called with len==0, but it would have been broken in that case. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* target: allow targets to override memory alignmentMathias K2011-03-172-4/+32
| | | | | Targets can implement read/write_buffer to handle alignment.
* SYS_WRITE0 fixJohn and Tina Peterson2011-03-171-1/+1
| | | | | | Problem is, trying to print "Hello, world!\n" just prints endless H's, because r1 is never incremented. One way to fix it would be to add a "++" after "r1".
* Fix a bunch of typos.Uwe Hermann2011-03-175-6/+6
| | | | | | | | Fix a bunch of typos. Most are in code comments, so nothing should break. UNKOWN_COMMAND and CMD_UNKOWN are not used elsewhere, so correcting the spelling should also not break anything.
* dsp563xx: fix alignment warningsØyvind Harboe2011-03-151-6/+6
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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