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* David Brownell <david-b@pacbell.net> fix warningsoharboe2009-08-281-4/+8
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2648 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* added arm11 timeout error messagesoharboe2009-08-283-11/+94
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2647 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* restore ICE watchpoint registers when the *last* software breakpoint is removedoharboe2009-08-282-3/+23
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2646 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> ARM disassembly support for about five ↵oharboe2009-08-281-6/+345
| | | | | | | | | | | | | | | | | | dozen non-Thumb instructions that were added after ARMv5TE was defined: - ARMv5J "BXJ" (for Java/Jazelle) - ARMv6 "media" instructions (for OMAP2420, i.MX31, etc) Compile-tested. This might not set up the simulator right for the ARMv6 single step support; only BXJ branches though, and docs to support Jazelle branching are non-public (still, sigh). ARMv6 instructions known to be mis-handled by this disassembler include: UMAAL, LDREX, STREX, CPS, SETEND, RFE, SRS, MCRR2, MRRC2 git-svn-id: svn://svn.berlios.de/openocd/trunk@2644 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* arm11 hardware step using simulation + breakpoint. Use "hardware_step ↵oharboe2009-08-271-19/+28
| | | | | | enable" command to revert to hardware stepping. Ideally we could retire the "hardware_step enable" command once we no longer believe it to be necessary. git-svn-id: svn://svn.berlios.de/openocd/trunk@2643 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* arm11 single stepping wip - at least we know the next PC nowoharboe2009-08-271-0/+4
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2642 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* arm11 single stepping wipoharboe2009-08-271-0/+101
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2641 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* refactor arm simulator to allow arm11 code to use it as well - no observable ↵oharboe2009-08-272-49/+147
| | | | | | changes otherwise. git-svn-id: svn://svn.berlios.de/openocd/trunk@2640 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ↵oharboe2009-08-261-5/+23
| | | | | | | | | cortex-a8: Wait for the CPU to be halted/started With DCCR we are asking the CPU to halt, we should wait until the CPU has halted before proceeding with the operation. git-svn-id: svn://svn.berlios.de/openocd/trunk@2638 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ↵oharboe2009-08-261-1/+1
| | | | | | Print the value that the method didn't like git-svn-id: svn://svn.berlios.de/openocd/trunk@2637 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ↵oharboe2009-08-261-1/+1
| | | | | | | | Only dap_ap_select when we are going to do a memory access in the fast reg case. git-svn-id: svn://svn.berlios.de/openocd/trunk@2636 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> cortex-a8: Copy some more registers from the ↵oharboe2009-08-261-0/+8
| | | | | | documentation git-svn-id: svn://svn.berlios.de/openocd/trunk@2635 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> cortex_a8_exec_opcode is writing the ARM ↵oharboe2009-08-261-1/+9
| | | | | | | | | | | instruction into the ITR register but it will only be executed when the DSCR[13] bit is set. The documentation is a bit weird as it classifies the DSCR as read-only but the pseudo code is writing to it as well. This is working on a beagleboard. git-svn-id: svn://svn.berlios.de/openocd/trunk@2634 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> Wait for the DTRRX to be full before reading it. ↵oharboe2009-08-261-4/+9
| | | | | | Remove the trans_mode change as it is done in the mem_ap_read_atomic_u32 function. git-svn-id: svn://svn.berlios.de/openocd/trunk@2633 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ↵oharboe2009-08-261-0/+8
| | | | | | | | | | Before executing a new instruction wait for the previous instruction to be finished. This comes from the pseudo code of the cortex a8 trm. git-svn-id: svn://svn.berlios.de/openocd/trunk@2632 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Remove bogus "BUG:". If the PC is pointing to an invalid instruction, then ↵oharboe2009-08-261-2/+2
| | | | | | simulation will fail. This is expected. git-svn-id: svn://svn.berlios.de/openocd/trunk@2629 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Tweak disassembly commands:oharboe2009-08-252-28/+55
| | | | | | | | | | | | | | | | | | For ARMv4/ARMv5: - better command parameter error checking - don't require an instruction count; default to one - recognize thumb function addresses - make function static - shorten some too-long lines For Cortex-M3: - don't require an instruction count; default to one With the relevant doc updates. --- Nyet done: invoke the thumb2 disassembler on v4/v5, to better handle branch instructions. git-svn-id: svn://svn.berlios.de/openocd/trunk@2624 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Accomodate targets which don't support ↵oharboe2009-08-251-0/+12
| | | | | | | | | | | | various target-specific reset operations. Maybe they can't; or it's a "not yet" thing. Note that the assert/deassert operations can't yet trigger for OMAP3 because resets currently include JTAG reset in all cases, resetting the ICEpick and thus disabling the TAP for Cortex-A8. git-svn-id: svn://svn.berlios.de/openocd/trunk@2620 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - fix build warningsntfreak2009-08-253-19/+19
| | | | | | - add svn props to recently added files armv7a.[ch] git-svn-id: svn://svn.berlios.de/openocd/trunk@2618 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* strange.... the code build and links w/Linux GCC target but fails w/arm-elf. ↵oharboe2009-08-251-3/+3
| | | | | | The code was clearly broken as it was missing two extern's in the .h file... git-svn-id: svn://svn.berlios.de/openocd/trunk@2616 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Ferdinand Postema <ferdinand@postema.eu> fix warningsoharboe2009-08-251-2/+2
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2615 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Michael Schwingen <rincewind@discworld.dascon.de> The attached patch adds a ↵oharboe2009-08-251-0/+63
| | | | | | | | | "xscale vector_table" command that allows to set the values that are written in the mini-IC (plus documentation updates that describe why this is needed). git-svn-id: svn://svn.berlios.de/openocd/trunk@2613 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell The rest of the Cortex-A8 support from Magnus: replace the ↵oharboe2009-08-252-88/+1358
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | previous nonfunctional cortex_a8 code with something that at least basically works (for halt/step/resume, without MMU) even if it is incomplete. (With tweaks from Øyvind, and cleanup from Dave.) This code has mainly been developed and tested against R1606, it has been built and tested against R2294 where it runs but step and resume commands are broken due to regression (which should be fixed now). This code is really written for OMAP3530. It doesn't identify debug resources using generic DAP calls to scan the ROM table, or perform topology detection. The OMAP3530 DAP exposes two memory access ports: - Port #0 is connected to L3 interconnect (the main bus) with passthrough to the L4 EMU bus ... so it will be used for most memory accesses. - Port #1 is connected to a dedicated debug bus (L4 EMU), with access to L4 Wakeup, and holds the ROM table ... so it must be used for most debug and control operations. The are some defines to handle this in cortex_a8.c, which should be replaced with more general code. Having access to another Cortex-A8 implementation would help get that right. git-svn-id: svn://svn.berlios.de/openocd/trunk@2609 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell Subset of Cortex-A8 support from Magnus: create an armv7a fileoharboe2009-08-253-0/+479
| | | | | | | | | | | | | | | | | | | and seed it with DAP access support using the current ADIv5 code. (With tweaks and cleanup from Øyvind and Dave.) The ARMv7-AR architecture manual is not publicly available (even in subset form like the ARMv7-M spec), so it's hard to distinguish between the Cortex-A8 implementation and the ARMv7-A architecture. The register set presumably is architectural, and so it's stored here; it's like earlier ARMs, with small additions. Ditto the instruction set, though Thumb2 support is used (extending Thumb support from ARMv6 with more 32-bit instructions) and there's this ThumbEE thing too. There is a new "debug monitor" mode, not yet fully addressed here, to support debugging in environments (like motor control) where halting debug mode is inadvisable. git-svn-id: svn://svn.berlios.de/openocd/trunk@2608 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Steve Grubb <sgrubb@redhat.com> fix various and sundry leaksoharboe2009-08-242-0/+13
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2606 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>More Thumb2 disassembly:oharboe2009-08-201-2/+136
| | | | | | | | | | | | | | | ARMv7-M: A5.3.6 Load/store dual or exclusive, table branch GCC will generate the table branch instructions, usually with inlined tables that will confuse this disassembler. LDREX and STREX are not issued by GCC without inline assembly. This means all Thumb2 instructions implemented by Cortex-M3 can now be disassembled. Cortex-A8 cores support more Thumb2 instructions, but most of those aren't yet publicly documented. git-svn-id: svn://svn.berlios.de/openocd/trunk@2598 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>Fix some command helptext:oharboe2009-08-191-4/+13
| | | | | | | | | - spell "address" right - list bp/wp params as optional And make those source lines wrap at sane margins. git-svn-id: svn://svn.berlios.de/openocd/trunk@2596 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Clean up some Cortex-M3 reset handling.oharboe2009-08-191-17/+39
| | | | | | | | | | | | | | - AIRCR_SYSRESETREQ is generic; use it on any system where SRST won't fly, not just on Stellaris-based ones. - Reformat and improve comments about the Stellaris quirk; and xref the only public docs (an email) about the issue. It seems that *most* Stellaris chips have this problem. Tempest parts aren't yet in general sampling; and if rev B silicon for earlier chips exists, it's not very visible yet. git-svn-id: svn://svn.berlios.de/openocd/trunk@2595 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell [david-b@pacbell.net]:ntfreak2009-08-181-10/+21
| | | | | | | | | | | | | Simplify dumping of register lists by only printing cached values if they are marked as valid. Most of the time, they are invalid; so printing *any* value is just misleading. Note that for ARM7 and ARM9 most EmbeddedICE registers (except for debug status) could be cached most of the time; and their register cache isn't maintained properly (many accesses seem to bypass that cache code). git-svn-id: svn://svn.berlios.de/openocd/trunk@2594 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Add "cortex_m3 vector_catch" command ↵oharboe2009-08-182-3/+83
| | | | | | | | | | | | | | | | and docs. One minor issue with this is that the core debug support uses this mechanism, then trashes its state over reset. Users can Work around that (for now) by re-assigning the desired config after reset. Also fixes "target halted due to target-not-halted" goof. When we can't describe the reason using OpenOCD's limited vocabulary, say "reason undefined" instead of saying it's not halted. git-svn-id: svn://svn.berlios.de/openocd/trunk@2588 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Clean up ARM7/ARM9 EmbeddedICE register ↵oharboe2009-08-182-49/+131
| | | | | | | | | | | | | | handling ... don't use parallel arrays (error prone) or assume all registers are 32-bits wide (they can have fewer bits); don't use spaces in register names, so they can be passed more easily to the "reg" command. Minor updates for ARM9 vector_catch support: it's an 8-bit value. This seems to help this core's vector_catch command work a bit better; but its behavior wih the register cache is still goofy. git-svn-id: svn://svn.berlios.de/openocd/trunk@2587 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Several of the ARMv7M registers are 8 ↵oharboe2009-08-181-29/+30
| | | | | | | | | bits or less; don't display them as 32 bits unless that's their true size. (Removes some confusion. git-svn-id: svn://svn.berlios.de/openocd/trunk@2586 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Ferdinand Postema <ferdinand@postema.eu> cygwin 32 bit warningoharboe2009-08-161-1/+1
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2581 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* added note w/reference to discussion on whether or not arm11 code is broken ↵oharboe2009-08-161-0/+4
| | | | | | or not. git-svn-id: svn://svn.berlios.de/openocd/trunk@2580 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Ferdinand Postema [ferdinand@postema.eu]ntfreak2009-08-071-0/+3
| | | | | | - fix vector catch issues with certain ARM9 cores - AT91SAM9260 and STR9 git-svn-id: svn://svn.berlios.de/openocd/trunk@2576 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - fix segfault introduced during cortex reg cleanupntfreak2009-08-071-2/+2
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2575 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* michal smulski <michal.smulski@ooma.com>:zwelch2009-08-061-2/+2
| | | | | | | Fix ARM11 half-word bulk memory read and write. git-svn-id: svn://svn.berlios.de/openocd/trunk@2572 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More testcase work:oharboe2009-07-261-7/+16
| | | | | | | | | | | | | | | | A5.3.11 Data processing (shifted register) The usual kinds of problems; the most noteworthy were that the "S"et flags bit was mis-handled in these instructions. --- This is the last patch from a quickie set of tests covering all encodings of the instructions with 32-bit opcodes. There may be some corner cases left, plus the instructions that aren't yet handled, but the Thumb2 disassembler is no longer just "lightly" tested with GCC output ... the new code paths have mostly been verified. git-svn-id: svn://svn.berlios.de/openocd/trunk@2568 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* More instruction decoding fixes:oharboe2009-07-261-16/+32
| | | | | | | | | | | A5.3.5 Load/store multiple A5.3.7 Load word There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM fixes are just using width specs to match UAL syntax, except for two opcode name typos. Load word had two bitmask goofs. git-svn-id: svn://svn.berlios.de/openocd/trunk@2567 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More fixes from test cases:oharboe2009-07-261-7/+11
| | | | | | | | | | A5.3.8 Load halfword, unallocated memory hints It's mostly the usual sort of bitmasking goofage and getting the width specs right. In one case an older x86 GCC generated bad code unless I structred a conditional differently (sigh). git-svn-id: svn://svn.berlios.de/openocd/trunk@2566 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More instruction decoding fixes:oharboe2009-07-261-8/+12
| | | | | | | | | | | A5.3.5 Load/store multiple A5.3.7 Load word There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM fixes are just using width specs to match UAL syntax, except for two opcode name typos. Load word had two bitmask goofs. git-svn-id: svn://svn.berlios.de/openocd/trunk@2565 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More instruction decoding fixes based ↵oharboe2009-07-241-9/+10
| | | | | | | | | | | | | | | | on test cases, covering ARMv7-M arch manual: A5.3.1 Data processing (modified immediate) A5.3.3 Data processing (plain binary immediate) A5.3.4 Branches and miscellaneous control and other (immediate) encodings referenced there. Several of these just tweak the new syntax ("Unified" ARM/Thumb: UAL) but there were a few bugs too. git-svn-id: svn://svn.berlios.de/openocd/trunk@2564 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Bugfix some instruction decoding ... ↵oharboe2009-07-241-4/+4
| | | | | | | | | | | | | | | | | I've crafted asm files with testcases covering several new encodings in these sections of the ARMv7-M arch manual: A5.3.12 Data processing (register) A5.3.13 Miscellaneous operations A5.3.14 Multiply, and multiply accumulate A5.3.15 Long multiply, long multiply accumulate, and divide The issues were mostly in '12 and '13; some new related 16-bit opcodes had issues too. git-svn-id: svn://svn.berlios.de/openocd/trunk@2563 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Andreas Fritiofson <andreas.fritiofson@gmail.com> I noticed there are a few ↵oharboe2009-07-241-10/+5
| | | | | | | | | checks for (rt == 0xf) even though that case is handled with an early return at the top of the function. git-svn-id: svn://svn.berlios.de/openocd/trunk@2562 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> thumb2 disassembly for Load halfwordoharboe2009-07-231-1/+86
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2561 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> thumb2 disassembly for Load byte, ↵oharboe2009-07-231-0/+170
| | | | | | memory hints git-svn-id: svn://svn.berlios.de/openocd/trunk@2560 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Ferdinand Postema <ferdinand@postema.eu> fix cygwin warningsoharboe2009-07-231-4/+4
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2559 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> fix warningsoharboe2009-07-231-44/+50
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2558 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:ntfreak2009-07-211-3/+10
| | | | | | | | | | | Dump SP on poll, and show whether it's MSP or PSP. Thread mode can use either stack pointer, so this is part of the state that's not yet displayed. Shrink some lines. git-svn-id: svn://svn.berlios.de/openocd/trunk@2555 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:ntfreak2009-07-213-104/+152
| | | | | | | | | | | | | | | | | | | | | | Clean up treatment of registers in ARMv7-M and Cortex-M3. - At the arch level: * Just list registers and names; don't impose core-specific policy about how they are accessed. * Each register has a symbol. * Remove the register mode field (irrelevant to debugger) - At the core/implementation level: * Just map the registers to their relevant access methods; don't require the arch level to say how that should work (cores other than Cortex-M3 could do it differently). * Don't use undefined bits from register 20. * Use register IDs that are part of the ARMv7-M interface. In short, there's now a real distinction between the arch and core layers. git-svn-id: svn://svn.berlios.de/openocd/trunk@2554 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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