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* Added CPUDBG_WCR_BASE definemlu2009-09-191-0/+1
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2734 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Avoid cache invalidation when writing to hardware debug registersmlu2009-09-191-4/+19
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2733 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Minor behavior fixes for the two JTAG reset events (C/internal,dbrownell2009-09-191-1/+2
| | | | | | | | | | | | | | | | | and Tcl/external): - Reorder so *both* paths (TCK/TMS or TRST) can enable TAPs with ICEpick ... first C code flags TAPs that got disabled, then call any Tcl code that might want to re-enable them. - Always call the C/internal handlers when JTAG operations can be issued; previously that wasn't done when TRST was used. Plus some small cleanups (whitespace, strings, better messaging during debug and on some errors) to reset-related code. git-svn-id: svn://svn.berlios.de/openocd/trunk@2730 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Move Cortex A8 debug access initialisation from omap3530.cfg to cortex_a8.cmlu2009-09-181-28/+39
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2728 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* srst_gates_jtag option. at91sam9260 needs retesting, and possibly ↵oharboe2009-09-171-1/+12
| | | | | | srst_gates_jtag added to reset_config. Could i.MX27 be a case where srst does not pull trst, but really srst gates jtag clock? git-svn-id: svn://svn.berlios.de/openocd/trunk@2720 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* The "arm9tdmi.c" file is more of a generic ARM9 support file:dbrownell2009-09-171-3/+17
| | | | | | | | | | | - update comments to say so. - update docs to clarify that the "arm9tdmi" command prefix is a misnomer. - bugfix some messages that wrongly assume only ARM9TDMI based processors use this code. git-svn-id: svn://svn.berlios.de/openocd/trunk@2719 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Remove unused varables (moved to armv7a)mlu2009-09-161-5/+0
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2717 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Use a variable armv7a->debug_base instead of hardedcoded OMAP3530_DEBUG_BASEmlu2009-09-161-28/+31
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2716 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Define debug_base, debug_ap, memory_ap in armv7a_common_tmlu2009-09-151-0/+7
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2714 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Updated mode string list.mlu2009-09-151-2/+2
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2713 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Definy symbolic values for VA to PA address translation operationsmlu2009-09-151-0/+10
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2712 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Check return values to avoid infinite wait in loop on error.mlu2009-09-141-4/+8
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2709 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Cache invalidation when writing to memorymlu2009-09-141-0/+18
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2708 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* More CortexA8 debug register definitions.mlu2009-09-131-0/+4
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2702 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Fix argument passing in cortex_a8_write_cp.mlu2009-09-131-2/+1
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2701 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> oharboe2009-09-123-26/+40
| | | | | | | | | | | | | | | Cleanup some the downloaded ARM target algorithm code: - Provide more complete disassembly of the DCC bulk write code - Make code blocks "static const", in case GCC doesn't - Fix some tabbing/layout issues - Make some arm7_9_common.h flags be "bool" not "int"; and compact the layout a bit (group most bools together) git-svn-id: svn://svn.berlios.de/openocd/trunk@2698 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Nicolas Pitre <nico@cam.org> put feroceon target definition at the end so to ↵oharboe2009-09-111-86/+79
| | | | | | | | avoid a bunch of useless forward declarations. git-svn-id: svn://svn.berlios.de/openocd/trunk@2694 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Nicolas Pitre <nico@cam.org> Dragonite supportoharboe2009-09-114-20/+76
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2693 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* spelling mistakeoharboe2009-09-111-2/+2
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2692 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* do not use dynamically sized stack arrays, not compatible with embedded OS'soharboe2009-09-111-10/+24
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2691 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* registering a target event twice caused infinite loop. Same bug as in ↵oharboe2009-09-111-4/+9
| | | | | | jtag/core.c copy & pasted. git-svn-id: svn://svn.berlios.de/openocd/trunk@2690 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Nicolas Pitre <nico@cam.org> tighten error checking in bulk_writeoharboe2009-09-111-4/+15
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2687 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Alexei Babich <a.babich@rez.ru> fix problems with unecessary tailend byte ↵oharboe2009-09-101-0/+12
| | | | | | accesses. Use 16 bit access on tailend of a memory read if possible. git-svn-id: svn://svn.berlios.de/openocd/trunk@2684 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> oharboe2009-09-094-4/+20
| | | | | | | | | | | | | | | | | Optionally shave time off the armv4_5 run_algorithm() code: let them terminate using software breakpoints, avoiding roundtrips to manage hardware ones. Enable this by using BKPT to terminate execution instead of "branch to here" loops. Then pass zero as the exit address, except when running on an ARMv4 core. ARM7TDMI, ARM9TDMI, and derived cores now set a flag saying they're ARMv4. Use that mechanism in arm_nandwrite(), for about 3% speedup on a DaVinci ARM926 core; not huge, but it helps. Some other algorithms could use this too (mostly flavors of flash operation). git-svn-id: svn://svn.berlios.de/openocd/trunk@2680 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Report correct core instruction state for ARMv/A targetsmlu2009-09-081-1/+1
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2678 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Load PC with bit 0 set to 1 when resuming to say in Thumb instruction state.mlu2009-09-081-2/+7
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2677 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> oharboe2009-09-081-0/+86
| | | | | | | | Provide an "armv7a disassemble" command. Current omissions include VFP (except as coprocessor instructions), Neon, and various Thumb2 opcodes that are not available in ARMv7-M processors. git-svn-id: svn://svn.berlios.de/openocd/trunk@2676 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> oharboe2009-09-081-35/+137
| | | | | | | | | | | | | | | | | | | | | lean up some loose ends with the ARM disassembler - Add a header comment describing its current state and uses and referencing the now-generally-available V7 arch spec - Support some mode switch instructions: * Thumb to Jazelle (BXJ) * Thumb to ThumbEE (ENTERX) * ThumbEE to Thumb (LEAVEX) - Improve that recent warning fix (and associated whitespace goof) - Declare the rest of the internal code and data "static". A compiler may use this, and it helps clarify the scope of these routines (e.g. what changes to them could affect). git-svn-id: svn://svn.berlios.de/openocd/trunk@2675 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Improved handling of instruction set state, helps for debugging Thumb state.mlu2009-09-071-7/+5
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2674 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Mahr, Stefan <Stefan.Mahr@sphairon.com> removes the endianness swapping in ↵oharboe2009-09-041-44/+0
| | | | | | mips_m4k.c Swapping is already done in target.c git-svn-id: svn://svn.berlios.de/openocd/trunk@2673 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> This patch simply enables the halting debug mode.oharboe2009-09-041-0/+7
| | | | | | | By enabling this bit, the processor halts when a debug event such as breakpoint occurs. git-svn-id: svn://svn.berlios.de/openocd/trunk@2668 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* more debug output for breakpointsoharboe2009-09-041-2/+10
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2667 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> Tidy up the bit-offset operation for DSCR registeroharboe2009-09-042-6/+15
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2666 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - fix a regression when using cortex_m3 emulated dcc channelntfreak2009-09-011-10/+19
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2659 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Warning fixduane2009-08-311-0/+3
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2658 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> start phasing out integers as target IDsoharboe2009-08-302-35/+22
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2650 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> fix warningsoharboe2009-08-281-4/+8
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2648 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* added arm11 timeout error messagesoharboe2009-08-283-11/+94
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2647 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* restore ICE watchpoint registers when the *last* software breakpoint is removedoharboe2009-08-282-3/+23
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2646 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> ARM disassembly support for about five ↵oharboe2009-08-281-6/+345
| | | | | | | | | | | | | | | | | | dozen non-Thumb instructions that were added after ARMv5TE was defined: - ARMv5J "BXJ" (for Java/Jazelle) - ARMv6 "media" instructions (for OMAP2420, i.MX31, etc) Compile-tested. This might not set up the simulator right for the ARMv6 single step support; only BXJ branches though, and docs to support Jazelle branching are non-public (still, sigh). ARMv6 instructions known to be mis-handled by this disassembler include: UMAAL, LDREX, STREX, CPS, SETEND, RFE, SRS, MCRR2, MRRC2 git-svn-id: svn://svn.berlios.de/openocd/trunk@2644 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* arm11 hardware step using simulation + breakpoint. Use "hardware_step ↵oharboe2009-08-271-19/+28
| | | | | | enable" command to revert to hardware stepping. Ideally we could retire the "hardware_step enable" command once we no longer believe it to be necessary. git-svn-id: svn://svn.berlios.de/openocd/trunk@2643 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* arm11 single stepping wip - at least we know the next PC nowoharboe2009-08-271-0/+4
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2642 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* arm11 single stepping wipoharboe2009-08-271-0/+101
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2641 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* refactor arm simulator to allow arm11 code to use it as well - no observable ↵oharboe2009-08-272-49/+147
| | | | | | changes otherwise. git-svn-id: svn://svn.berlios.de/openocd/trunk@2640 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ↵oharboe2009-08-261-5/+23
| | | | | | | | | cortex-a8: Wait for the CPU to be halted/started With DCCR we are asking the CPU to halt, we should wait until the CPU has halted before proceeding with the operation. git-svn-id: svn://svn.berlios.de/openocd/trunk@2638 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ↵oharboe2009-08-261-1/+1
| | | | | | Print the value that the method didn't like git-svn-id: svn://svn.berlios.de/openocd/trunk@2637 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ↵oharboe2009-08-261-1/+1
| | | | | | | | Only dap_ap_select when we are going to do a memory access in the fast reg case. git-svn-id: svn://svn.berlios.de/openocd/trunk@2636 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> cortex-a8: Copy some more registers from the ↵oharboe2009-08-261-0/+8
| | | | | | documentation git-svn-id: svn://svn.berlios.de/openocd/trunk@2635 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> cortex_a8_exec_opcode is writing the ARM ↵oharboe2009-08-261-1/+9
| | | | | | | | | | | instruction into the ITR register but it will only be executed when the DSCR[13] bit is set. The documentation is a bit weird as it classifies the DSCR as read-only but the pseudo code is writing to it as well. This is working on a beagleboard. git-svn-id: svn://svn.berlios.de/openocd/trunk@2634 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Matt Hsu <matt@0xlab.org> Wait for the DTRRX to be full before reading it. ↵oharboe2009-08-261-4/+9
| | | | | | Remove the trans_mode change as it is done in the mem_ap_read_atomic_u32 function. git-svn-id: svn://svn.berlios.de/openocd/trunk@2633 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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