| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
| |
fixup fastdata
|
| |
|
| |
|
| |
|
|
|
|
| |
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
|
|
|
|
|
|
|
| |
cygwin does not define sleep, so use our internal win32 version.
caused by commit 9d4aec6bda90ad39a140747ea270c6a09dd26440
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
|
| |
|
| |
|
| |
|
|
|
|
|
|
| |
Conflicts:
src/target/cortex_a.c
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
- works on Cortex-M3 with ThreadX and FreeRTOS
Compared to original patch a few nits were fixed:
- remove stricmp usage
- unsigned compare fix
- printf formatting fixes
- fixed a bug with overrunning a memory buffer allocated with malloc.
|
|
|
|
|
|
|
|
|
| |
Freescale iMX53 doesn't seem to like unaligned accesses to his memory
mapped registers.
Anyway this patch makes dump_image/load_image 4X faster for every
access through APB.
Signed-off-by: Luca Ellero <lroluk@gmail.com>
|
|
|
|
| |
Signed-off-by: Luca Ellero <lroluk@gmail.com>
|
|
|
|
|
|
| |
Conflicts:
src/target/cortex_a.c
|
| |
|
| |
|
| |
|
| |
|
|
|
|
| |
that PrAcc is "1" before FASTDATA access.
|
|
|
|
| |
to use mips_m4k_write_memory() and mips_m4k_read_memory() to correctly set-up SDRAM, as well as bulk data write, which already handled endianess well. Also added correct endianess manipulation in case of fallback from erroneus bulk write to simple write (to avoid byte swapping two times).
|
|
|
|
| |
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
| |
|
|\ |
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
the patchup code would get false positives when checking
whether a dbgbase had to be corrected.
The solution is to have autodetect default, with manual override
in scripts.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
| |
| |
| |
| |
| |
| |
| | |
Do not require unecessary roundtrips for clocking out
data.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
| |
| |
| |
| | |
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
| |
| |
| |
| |
| |
| |
| |
| | |
Could this cause confusion as data sent to write would be flipped
and then if the caller subsequently used the data, e.g. a
compare mismatch might happen?
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
| |
| |
| |
| | |
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
| |
| |
| |
| | |
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
| |
| |
| |
| |
| |
| | |
this fn does not fail, it queues data.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
|/
|
|
|
|
|
|
| |
accidentally invoked return jtag_execute_queue() in the
middle of a fn. Hmm.... I would have expected gcc or
at least lint to catch this.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
|
|
|
| |
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
|
|
|
|
|
|
| |
it would *read* instead of *write* to memory
when the MMU was disabled.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
|
|
|
| |
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
|
|
|
|
|
|
|
|
| |
Really a Cortex-A specific option, but there is no
system in place to support target specific options
currently and there has been no need for such a system
until now.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
|
|
|
|
|
|
|
|
| |
The patch below fixes step <address> on mips_m4k.
Spencer Oliver <spen@spen-soft.co.uk>:
The current code is used on all other arch's - is
there a underlying issue with those aswell ?
|
|
|
|
| |
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
|
|
|
| |
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
|
|
|
|
|
| |
better to keep this in a single file.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
|
|
|
|
|
|
|
| |
I don't think dsp563xx_once_read_register() would ever
be called with len==0, but it would have been broken in
that case.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
|
|
|
|
| |
Targets can implement read/write_buffer to handle
alignment.
|
|
|
|
|
|
| |
Problem is, trying to print "Hello, world!\n" just prints endless H's, because r1 is never incremented.
One way to fix it would be to add a "++" after "r1".
|
|
|
|
|
|
|
|
| |
Fix a bunch of typos.
Most are in code comments, so nothing should break. UNKOWN_COMMAND and
CMD_UNKOWN are not used elsewhere, so correcting the spelling should
also not break anything.
|
|
|
|
| |
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
|
|
|
|
|
| |
found by inspection.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
|
|
|
|
|
|
|
| |
add new mem_ap_sel_* functions (as was made for cortex_a9)
see commit: 779005f43dc372de937dfd4b445f31d882b98eca
Signed-off-by: Luca Ellero <lroluk@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
| |
This patch add rudimentary gdb support. The gdb register list
order is corrected. All registers are now 32bit width. Events are
send to signalize gdb the current target status. Resume and step
function was corrected to consider a modified pc register. Read/write
memory now support L memory type, this means a memory with alternating
y/x memory words. The memspace variable, used by gdb, is now observed
before a default memory access is initiated. Dummy functions for breakpoint
and watchpoint are added.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This patch tries to make some order in "apsel" mess.
"dap apsel" command was quite useless (and broken) by itself.
With this patch we can use it to select between AHB or APB memory access
(previous patch 05ab8bdb813acdcd74afa71d6656c2df816cb230 was somehow broken).
- moves member apsel (in struct adiv5_dap) to ap_current
- adds apsel member
this strange choice is made trying to keep coherence in "dap apsel" command
and to keep compatibility with other code (for example cortex_a8).
Signed-off-by: Luca Ellero <lroluk@gmail.com>
|
|
|
|
|
|
|
|
| |
This patch move the dsp563xx_target_create function to the
related code block. Also the target examine function was added
and the register cache is initialized in a separate function. The
missing functionality to invalidate the x memory context on memory
writes was also added.
|