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* David Brownell Subset of Cortex-A8 support from Magnus: create an armv7a fileoharboe2009-08-253-0/+479
| | | | | | | | | | | | | | | | | | | and seed it with DAP access support using the current ADIv5 code. (With tweaks and cleanup from Øyvind and Dave.) The ARMv7-AR architecture manual is not publicly available (even in subset form like the ARMv7-M spec), so it's hard to distinguish between the Cortex-A8 implementation and the ARMv7-A architecture. The register set presumably is architectural, and so it's stored here; it's like earlier ARMs, with small additions. Ditto the instruction set, though Thumb2 support is used (extending Thumb support from ARMv6 with more 32-bit instructions) and there's this ThumbEE thing too. There is a new "debug monitor" mode, not yet fully addressed here, to support debugging in environments (like motor control) where halting debug mode is inadvisable. git-svn-id: svn://svn.berlios.de/openocd/trunk@2608 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Steve Grubb <sgrubb@redhat.com> fix various and sundry leaksoharboe2009-08-242-0/+13
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2606 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>More Thumb2 disassembly:oharboe2009-08-201-2/+136
| | | | | | | | | | | | | | | ARMv7-M: A5.3.6 Load/store dual or exclusive, table branch GCC will generate the table branch instructions, usually with inlined tables that will confuse this disassembler. LDREX and STREX are not issued by GCC without inline assembly. This means all Thumb2 instructions implemented by Cortex-M3 can now be disassembled. Cortex-A8 cores support more Thumb2 instructions, but most of those aren't yet publicly documented. git-svn-id: svn://svn.berlios.de/openocd/trunk@2598 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>Fix some command helptext:oharboe2009-08-191-4/+13
| | | | | | | | | - spell "address" right - list bp/wp params as optional And make those source lines wrap at sane margins. git-svn-id: svn://svn.berlios.de/openocd/trunk@2596 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Clean up some Cortex-M3 reset handling.oharboe2009-08-191-17/+39
| | | | | | | | | | | | | | - AIRCR_SYSRESETREQ is generic; use it on any system where SRST won't fly, not just on Stellaris-based ones. - Reformat and improve comments about the Stellaris quirk; and xref the only public docs (an email) about the issue. It seems that *most* Stellaris chips have this problem. Tempest parts aren't yet in general sampling; and if rev B silicon for earlier chips exists, it's not very visible yet. git-svn-id: svn://svn.berlios.de/openocd/trunk@2595 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell [david-b@pacbell.net]:ntfreak2009-08-181-10/+21
| | | | | | | | | | | | | Simplify dumping of register lists by only printing cached values if they are marked as valid. Most of the time, they are invalid; so printing *any* value is just misleading. Note that for ARM7 and ARM9 most EmbeddedICE registers (except for debug status) could be cached most of the time; and their register cache isn't maintained properly (many accesses seem to bypass that cache code). git-svn-id: svn://svn.berlios.de/openocd/trunk@2594 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Add "cortex_m3 vector_catch" command ↵oharboe2009-08-182-3/+83
| | | | | | | | | | | | | | | | and docs. One minor issue with this is that the core debug support uses this mechanism, then trashes its state over reset. Users can Work around that (for now) by re-assigning the desired config after reset. Also fixes "target halted due to target-not-halted" goof. When we can't describe the reason using OpenOCD's limited vocabulary, say "reason undefined" instead of saying it's not halted. git-svn-id: svn://svn.berlios.de/openocd/trunk@2588 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Clean up ARM7/ARM9 EmbeddedICE register ↵oharboe2009-08-182-49/+131
| | | | | | | | | | | | | | handling ... don't use parallel arrays (error prone) or assume all registers are 32-bits wide (they can have fewer bits); don't use spaces in register names, so they can be passed more easily to the "reg" command. Minor updates for ARM9 vector_catch support: it's an 8-bit value. This seems to help this core's vector_catch command work a bit better; but its behavior wih the register cache is still goofy. git-svn-id: svn://svn.berlios.de/openocd/trunk@2587 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Several of the ARMv7M registers are 8 ↵oharboe2009-08-181-29/+30
| | | | | | | | | bits or less; don't display them as 32 bits unless that's their true size. (Removes some confusion. git-svn-id: svn://svn.berlios.de/openocd/trunk@2586 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Ferdinand Postema <ferdinand@postema.eu> cygwin 32 bit warningoharboe2009-08-161-1/+1
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2581 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* added note w/reference to discussion on whether or not arm11 code is broken ↵oharboe2009-08-161-0/+4
| | | | | | or not. git-svn-id: svn://svn.berlios.de/openocd/trunk@2580 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Ferdinand Postema [ferdinand@postema.eu]ntfreak2009-08-071-0/+3
| | | | | | - fix vector catch issues with certain ARM9 cores - AT91SAM9260 and STR9 git-svn-id: svn://svn.berlios.de/openocd/trunk@2576 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - fix segfault introduced during cortex reg cleanupntfreak2009-08-071-2/+2
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2575 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* michal smulski <michal.smulski@ooma.com>:zwelch2009-08-061-2/+2
| | | | | | | Fix ARM11 half-word bulk memory read and write. git-svn-id: svn://svn.berlios.de/openocd/trunk@2572 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More testcase work:oharboe2009-07-261-7/+16
| | | | | | | | | | | | | | | | A5.3.11 Data processing (shifted register) The usual kinds of problems; the most noteworthy were that the "S"et flags bit was mis-handled in these instructions. --- This is the last patch from a quickie set of tests covering all encodings of the instructions with 32-bit opcodes. There may be some corner cases left, plus the instructions that aren't yet handled, but the Thumb2 disassembler is no longer just "lightly" tested with GCC output ... the new code paths have mostly been verified. git-svn-id: svn://svn.berlios.de/openocd/trunk@2568 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* More instruction decoding fixes:oharboe2009-07-261-16/+32
| | | | | | | | | | | A5.3.5 Load/store multiple A5.3.7 Load word There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM fixes are just using width specs to match UAL syntax, except for two opcode name typos. Load word had two bitmask goofs. git-svn-id: svn://svn.berlios.de/openocd/trunk@2567 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More fixes from test cases:oharboe2009-07-261-7/+11
| | | | | | | | | | A5.3.8 Load halfword, unallocated memory hints It's mostly the usual sort of bitmasking goofage and getting the width specs right. In one case an older x86 GCC generated bad code unless I structred a conditional differently (sigh). git-svn-id: svn://svn.berlios.de/openocd/trunk@2566 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More instruction decoding fixes:oharboe2009-07-261-8/+12
| | | | | | | | | | | A5.3.5 Load/store multiple A5.3.7 Load word There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM fixes are just using width specs to match UAL syntax, except for two opcode name typos. Load word had two bitmask goofs. git-svn-id: svn://svn.berlios.de/openocd/trunk@2565 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> More instruction decoding fixes based ↵oharboe2009-07-241-9/+10
| | | | | | | | | | | | | | | | on test cases, covering ARMv7-M arch manual: A5.3.1 Data processing (modified immediate) A5.3.3 Data processing (plain binary immediate) A5.3.4 Branches and miscellaneous control and other (immediate) encodings referenced there. Several of these just tweak the new syntax ("Unified" ARM/Thumb: UAL) but there were a few bugs too. git-svn-id: svn://svn.berlios.de/openocd/trunk@2564 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> Bugfix some instruction decoding ... ↵oharboe2009-07-241-4/+4
| | | | | | | | | | | | | | | | | I've crafted asm files with testcases covering several new encodings in these sections of the ARMv7-M arch manual: A5.3.12 Data processing (register) A5.3.13 Miscellaneous operations A5.3.14 Multiply, and multiply accumulate A5.3.15 Long multiply, long multiply accumulate, and divide The issues were mostly in '12 and '13; some new related 16-bit opcodes had issues too. git-svn-id: svn://svn.berlios.de/openocd/trunk@2563 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Andreas Fritiofson <andreas.fritiofson@gmail.com> I noticed there are a few ↵oharboe2009-07-241-10/+5
| | | | | | | | | checks for (rt == 0xf) even though that case is handled with an early return at the top of the function. git-svn-id: svn://svn.berlios.de/openocd/trunk@2562 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> thumb2 disassembly for Load halfwordoharboe2009-07-231-1/+86
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2561 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> thumb2 disassembly for Load byte, ↵oharboe2009-07-231-0/+170
| | | | | | memory hints git-svn-id: svn://svn.berlios.de/openocd/trunk@2560 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Ferdinand Postema <ferdinand@postema.eu> fix cygwin warningsoharboe2009-07-231-4/+4
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2559 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> fix warningsoharboe2009-07-231-44/+50
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2558 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:ntfreak2009-07-211-3/+10
| | | | | | | | | | | Dump SP on poll, and show whether it's MSP or PSP. Thread mode can use either stack pointer, so this is part of the state that's not yet displayed. Shrink some lines. git-svn-id: svn://svn.berlios.de/openocd/trunk@2555 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:ntfreak2009-07-213-104/+152
| | | | | | | | | | | | | | | | | | | | | | Clean up treatment of registers in ARMv7-M and Cortex-M3. - At the arch level: * Just list registers and names; don't impose core-specific policy about how they are accessed. * Each register has a symbol. * Remove the register mode field (irrelevant to debugger) - At the core/implementation level: * Just map the registers to their relevant access methods; don't require the arch level to say how that should work (cores other than Cortex-M3 could do it differently). * Don't use undefined bits from register 20. * Use register IDs that are part of the ARMv7-M interface. In short, there's now a real distinction between the arch and core layers. git-svn-id: svn://svn.berlios.de/openocd/trunk@2554 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:ntfreak2009-07-211-11/+18
| | | | | | | | | | | | | | | Minor updates to the Thumb2 disassembly: - Bugfixes: * Distinguish branch from misc via "!=" not "==" * MRS register shift is 8 bits (vs MSR being 16) - Format tweaks: * CPS needed tab (not space) * add commma before some shifts * add space after comma in LDM/STM * use ".W" width spec on various instructions git-svn-id: svn://svn.berlios.de/openocd/trunk@2553 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:ntfreak2009-07-214-75/+32
| | | | | | | | | Revert parts of the previous ARMv7-M register patch. It turns out that part of the issue is a documentation problem for the Cortex-M3 r1 parts. So for the rest, simpler fixes are possible (in followup patch). git-svn-id: svn://svn.berlios.de/openocd/trunk@2552 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Andreas Fritiofson <andreas.fritiofson@gmail.com> UTF8 fixesoharboe2009-07-1719-19/+19
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2549 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* microscopic whitespace cleanupoharboe2009-07-161-15/+0
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2547 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* microscopic white space fixesoharboe2009-07-161-16/+0
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2546 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>, ↵zwelch2009-07-163-88/+148
| | | | | | | | | | | | | | David Brownell <david-b@pacbell.net>: Move the dap command handler implementations to arm_adi_v5.c, leaving just thin wrappers in armv7m.c. There should be no change in functionality here. (From Magnus.) Minor style cleanup: whitespace, line length, etc. Update spec references to use docs which are currently available. (From Dave.) git-svn-id: svn://svn.berlios.de/openocd/trunk@2544 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>, ↵zwelch2009-07-164-35/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | David Brownell <david-b@pacbell.net>: Some cleanup of the ARMv7-M support: - Reference the relevant ARMv7-M ARM doc (DDI 0405C to non-Vendors), and update the Cortex-M3 doc refs (DDI 0337C is no longer available). - Those registers aren't actually general, and some are incorrect (per all public docs anyway). Update comments and code accordingly. * What the Core Debug facility exposes is *implementation-specific* not architectural. These values aren't fully portable. They match Cortex-M3 ... so no current implementation will make trouble, but the next v7m implementation might. * Four of the registers are actually not exposed that way. Before Cortex-M3 r2p0 they are read/written through MRS/MSR instructions. In that newest silicon, they are four bytes in one register, not four separate registers. - Update the CM3 code to report when that one register is available, and not try to access it when it isn't. Also declare the register numbers that an eventual MRS/MSR solution will need to be using. - Stop line wrapping the exception labels. So for parts before r2p0 OpenOCD behavior is effectively unchanged, and still buggy; but for those newer parts a few things might now be correct. Most current Cortex-M3 parts use r1p1 (or earlier); this seems to include most LM3S parts and all STM32 parts. Parts using r2p0 are available, and include fourth generation LM3S parts ("Tempest") plus AT91SAM3 and LPC17xx parts which are now sampling. git-svn-id: svn://svn.berlios.de/openocd/trunk@2543 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:zwelch2009-07-151-0/+78
| | | | | | | | | More 32-bit Thumb2 instruction decoding: A5.3.7 Load word git-svn-id: svn://svn.berlios.de/openocd/trunk@2542 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:zwelch2009-07-151-0/+105
| | | | | | | | | More 32-bit Thumb2 instruction decoding: A5.3.12 Data processing (register) git-svn-id: svn://svn.berlios.de/openocd/trunk@2541 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:zwelch2009-07-151-0/+168
| | | | | | | | | More 32-bit instruction decoding: A5.3.11 Data processing (shifted register) git-svn-id: svn://svn.berlios.de/openocd/trunk@2540 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:zwelch2009-07-151-0/+53
| | | | | | | | | | | More instructions decoded: A5.3.5 Load/store multiple The preferred PUSH/POP syntax is shown when appropriate. git-svn-id: svn://svn.berlios.de/openocd/trunk@2539 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:zwelch2009-07-151-0/+73
| | | | | | | | | | | | | More instructions decoded: A5.3.14 Multiply, and multiply accumulate A5.3.15 Long multiply, long multiply accumulate, divide The EABI requires *adjacent* register pairs, but the long multiply ops can use any pair of registers; interesting. git-svn-id: svn://svn.berlios.de/openocd/trunk@2538 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:zwelch2009-07-151-0/+96
| | | | | | | | | | | | | More Thumb2 32-bit opcode support: A5.3.10 Store single data item Byte, word, halfword. Offset, pre-index, post-index. And a "make like you're unprivileged" option when using small immediate offsets. git-svn-id: svn://svn.berlios.de/openocd/trunk@2537 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:zwelch2009-07-151-3/+12
| | | | | | | | Print old-style Thumb NOP instructions as such. (GCC uses "mov r8, r8" instead of the architected NOP which is new in Thumb2.) git-svn-id: svn://svn.berlios.de/openocd/trunk@2536 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:zwelch2009-07-151-7/+15
| | | | | | | | | Make disassembly of the Thumb load-literal instruction show the address of the literal being loaded (so users can avoid doing that math themselves). Add and use an Align(PC,4) utility. git-svn-id: svn://svn.berlios.de/openocd/trunk@2535 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:zwelch2009-07-151-0/+99
| | | | | | | | | | | | Make the Thumb2 disassembler handle more 32-bit instructions: A5.3.3 Data processing (plain binary immediate) These use mostly twelve bit literals, but there are also bitfield and saturated add primitives. git-svn-id: svn://svn.berlios.de/openocd/trunk@2534 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:zwelch2009-07-151-1/+143
| | | | | | | | | | | Make the Thumb2 disassembler handle more 32-bit instructions: A5.3.1 Data processing (modified immediate) My small sample shows GCC likes to use many of these instructions. git-svn-id: svn://svn.berlios.de/openocd/trunk@2533 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:zwelch2009-07-151-4/+263
| | | | | | | | | | | | | | | | | Make the Thumb2 disassembler handle a bunch of 32-bit instructions: A5.3.4 Branches and miscellaneous control Note that this shifts some responsabililty out of helper functions, making the code and layout simpler for 32-bit decoders: they only need to know how to format the instruction and its parameters. Also, technical note: with this patch, Thumb1 decoders could now call the Thumb2 decoder if they wanted to get nicer treatment of the exiting 32-bit B/BLX instructions. git-svn-id: svn://svn.berlios.de/openocd/trunk@2532 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:zwelch2009-07-151-37/+77
| | | | | | | | | | | | | | | | | | | | | | | Change layout of Thumb disassembly to work better with Thumb2: - Move opcode to the left, allowing space for four hex bytes: * after address, two spaces not one tab (taking 6 spaces) * after 2-byte opcode, four spaces before tab - Also, after opcode mnemonic use a tab not a space, to make operands line up Sample output (after some patches decoding a few 32-bit instructions): 0x00003e5a 0xf4423200 ORR r2, r2, #131072 ; 0x20000 0x00003e5e 0x601a STR r2, [r3, #0x0] 0x00003e60 0x2800 CMP r0, #0x00 0x00003e62 0xd1f3 BNE 0x00003e4c 0x00003e64 0xf008fa38 BL 0x0000c2d8 The affected lines of code now wrap at sane margins too. git-svn-id: svn://svn.berlios.de/openocd/trunk@2531 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:zwelch2009-07-153-17/+295
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initial support for disassembling Thumb2 code. This works only for Cortex-M3 cores so far. Eventually other cores will also need Thumb2 support ... but they don't yet support any kind of disassembly. - Update the 16-bit Thumb decoder: * Understand CPS, REV*, SETEND, {U,S}XT{B,H} opcodes added by ARMv6. (It already seems to treat CPY as MOV.) * Understand CB, CBNZ, WFI, IT, and other opcodes added by in Thumb2. - A new Thumb2 instruction decode routine is provided. * This has a different signature: pass the target, not the instruction, so it can fetch a second halfword when needed. The instruction size is likewise returned to the caller. * 32-bit instructions are recognized but not yet decoded. - Start using the current "UAL" syntax in some cases. "SWI" is renamed as "SVC"; "LDMIA" as "LDM"; "STMIA" as "STM". - Define a new "cortex_m3 disassemble addr count" command to give access to this disassembly. Sanity checked against "objdump -d" output; a bunch of the new instructions checked out fine. git-svn-id: svn://svn.berlios.de/openocd/trunk@2530 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Magnus Lundin Thc cortex_m3_poll function does not identify that a target ↵oharboe2009-07-121-9/+12
| | | | | | | | | | | is running unless we transition from RESET. This patch correctly identifies a running target. Patch made a tad more palatable by David Brownell <david-b@pacbell.net> git-svn-id: svn://svn.berlios.de/openocd/trunk@2510 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* more debug output for translation of arm mode number to enumoharboe2009-07-061-1/+1
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2481 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* a bit more debug output for translation of invalid mode numbersoharboe2009-07-061-1/+1
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2480 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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