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author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-05-19 19:02:36 +0000 |
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committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-05-19 19:02:36 +0000 |
commit | 05d143857ccadfa2ab3a9bf11461482f8e3a53b7 (patch) | |
tree | 74d470eae70edac2e4cb4836d3a88770bc1a9dc7 | |
parent | a76c3433e1720a5e1d503c51c5b68e2884cf7522 (diff) | |
download | openocd_libswd-05d143857ccadfa2ab3a9bf11461482f8e3a53b7.tar.gz openocd_libswd-05d143857ccadfa2ab3a9bf11461482f8e3a53b7.tar.bz2 openocd_libswd-05d143857ccadfa2ab3a9bf11461482f8e3a53b7.tar.xz openocd_libswd-05d143857ccadfa2ab3a9bf11461482f8e3a53b7.zip |
Fix crash when mode number fetched from the target is invalid.
git-svn-id: svn://svn.berlios.de/openocd/trunk@667 b42882b7-edfa-0310-969c-e2dbd0fdcd60
-rw-r--r-- | src/target/arm7_9_common.c | 28 | ||||
-rw-r--r-- | src/target/arm920t.c | 12 | ||||
-rw-r--r-- | src/target/armv4_5.c | 9 | ||||
-rw-r--r-- | src/target/xscale.c | 4 |
4 files changed, 53 insertions, 0 deletions
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 61484ccc..740cf923 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -903,6 +903,9 @@ int arm7_9_soft_reset_halt(struct target_s *target) armv4_5->core_mode = ARMV4_5_MODE_SVC; armv4_5->core_state = ARMV4_5_STATE_ARM; + + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; /* reset registers */ for (i = 0; i <= 14; i++) @@ -1091,6 +1094,8 @@ int arm7_9_debug_entry(target_t *target) LOG_ERROR("unknown debug reason: %i", target->debug_reason); } + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; for (i=0; i<=15; i++) { @@ -1101,6 +1106,9 @@ int arm7_9_debug_entry(target_t *target) } LOG_DEBUG("entered debug state at PC 0x%x", context[15]); + + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; /* exceptions other than USR & SYS have a saved program status register */ if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS)) @@ -1140,6 +1148,9 @@ int arm7_9_full_context(target_t *target) LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } + + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND) * SYS shares registers with User, so we don't touch SYS @@ -1226,6 +1237,9 @@ int arm7_9_restore_context(target_t *target) if (arm7_9->pre_restore_context) arm7_9->pre_restore_context(target); + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND) * SYS shares registers with User, so we don't touch SYS */ @@ -1635,6 +1649,10 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod int retval; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; + + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode; if ((num < 0) || (num > 16)) @@ -1696,6 +1714,10 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo u32 reg[16]; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; + + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode; if ((num < 0) || (num > 16)) @@ -1871,6 +1893,9 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count break; } + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + for (i=0; i<=last_reg; i++) ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid; @@ -2038,6 +2063,9 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1); embeddedice_store_reg(dbg_ctrl); + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + for (i=0; i<=last_reg; i++) ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid; diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 2dff6b94..9e9bf1a5 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -335,6 +335,9 @@ int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value); #endif + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1; @@ -370,6 +373,9 @@ int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value, LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address); #endif + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1; @@ -1000,6 +1006,9 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c fclose(output); + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + /* mark registers dirty. */ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid; @@ -1261,6 +1270,9 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd fclose(output); + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + /* mark registers dirty */ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid; diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index 264a4437..e546e404 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -329,6 +329,9 @@ int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, cha return ERROR_OK; } + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + for (num = 0; num <= 15; num++) { output_len = 0; @@ -441,6 +444,9 @@ int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list armv4_5_common_t *armv4_5 = target->arch_info; int i; + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + *reg_list_size = 26; *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size)); @@ -485,6 +491,9 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param return ERROR_TARGET_NOT_HALTED; } + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + for (i = 0; i <= 16; i++) { if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid) diff --git a/src/target/xscale.c b/src/target/xscale.c index 7762ec2a..48233243 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -1091,6 +1091,10 @@ int xscale_debug_entry(target_t *target) else armv4_5->core_state = ARMV4_5_STATE_ARM; + + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */ if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS)) { |