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authorDean Glazeski <dnglaze@gmail.com>2009-10-18 22:26:38 +0200
committerØyvind Harboe <oyvind.harboe@zylin.com>2009-10-18 22:26:38 +0200
commit76b4ee8935c86466895b0cbf070389337581d593 (patch)
tree69a2b44d262164c58b712e14477db708120d530d
parent990f50a73bca9f9fe4f261161b25fb8fb4432e52 (diff)
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SDRAM and clock configuration for the SAM9-L9260 board from Olimex
-rw-r--r--tcl/board/olimex_sam9_l9260.cfg91
1 files changed, 85 insertions, 6 deletions
diff --git a/tcl/board/olimex_sam9_l9260.cfg b/tcl/board/olimex_sam9_l9260.cfg
index fbd8f5c0..b5cd10ec 100644
--- a/tcl/board/olimex_sam9_l9260.cfg
+++ b/tcl/board/olimex_sam9_l9260.cfg
@@ -1,10 +1,89 @@
-##
-# Olimex SAM9-L9260 board configuration file
+################################################################################
+# Olimex SAM9-L9260 Development Board
#
-# Date Author Change
-# ---- ----- -----
-# 17/Jan/2009 Dean Glazeski Initial Creation
+# http://www.olimex.com/dev/sam9-L9260.html
#
-##
+# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
+# PMC configured for external 18.432 MHz crystal
+#
+# 32-bit SDRAM : 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks
+# 8-bit NAND Flash : 1 x Samsung K9F4G08U0M, 512M x 8Bit
+# Dataflash : 1 x Atmel AT45DB161D, 16Mbit
+#
+################################################################################
source [find target/at91sam9260.cfg]
+
+# NTRST_E jumper is enabled by default, so we don't need to override the reset
+# config.
+#reset_config srst_only
+
+$_TARGETNAME configure -event reset-start {
+ # At reset, CPU runs at 32.768 kHz. JTAG frequency must be 6 times slower if
+ # RCLK is not supported.
+ jtag_rclk 5
+ halt
+
+ # RSTC_MR : enable user reset, reset length is 64 slow clock cycles. MMU may
+ # be enabled... use physical address.
+ arm926ejs mww_phys 0xfffffd08 0xa5000501
+}
+
+$_TARGETNAME configure -event reset-init {
+ mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
+
+ ##
+ # Clock configuration for 99.328 MHz main clock.
+ ##
+ mww 0xfffffc20 0x00004001 # CKGR_MOR : enable main oscillator, 512 slow clock startup
+ sleep 20 # wait 20 ms (need 15.6 ms for startup)
+ mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator (18.432 MHz)
+ sleep 10 # wait 10 ms
+ mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR : 18.432 MHz / 9 * 97 = 198.656 MHz, 63 slow clock startup
+ sleep 20 # wait 20 ms (need 1.9 ms for startup)
+ mww 0xfffffc30 0x00000101 # PMC_MCKR : no scale on proc clock, master is proc / 2
+ sleep 10 # wait 10 ms
+ mww 0xfffffc30 0x00000102 # PMC_MCKR : switch to PLLA (99.328 MHz)
+
+ # Increase JTAG speed to 6 MHz if RCLK is not supported.
+ jtag_rclk 6000
+
+ arm7_9 dcc_downloads enable # Enable faster DCC downloads.
+
+ ##
+ # SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks.
+ ##
+ mww 0xfffff870 0xffff0000 # PIOC_ASR : select peripheral function for D15..D31
+ mww 0xfffff804 0xffff0000 # PIOC_PDR : disable PIO function for D15..D31
+
+ mww 0xffffef1c 0x00010002 # EBI_CSA : assign EBI CS1 to SDRAM, VDDIOMSEL set for +3V3 memory
+
+ mww 0xffffea08 0x85237259 # SDRAMC_CR : configure SDRAM for Samsung chips
+
+ mww 0xffffea00 0x1 # SDRAMC_MR : issue NOP command
+ mww 0x20000000 0
+ mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
+ mww 0x20000000 0
+ mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' command
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
+ mww 0x20000000 0
+ mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
+ mww 0x20000000 0
+
+ mww 0xffffea04 0x2b6 # SDRAMC_TR : set refresh timer count to 7 us
+}