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author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-07-22 14:25:56 +0000 |
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committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-07-22 14:25:56 +0000 |
commit | a7a1ae032ba4c300413c46880ff81f2b187f570b (patch) | |
tree | 48fac96e24d3e62c07289ea9c9b3afcd1a11bb21 | |
parent | d460a7cd6cc218bd4c3cc8a98ba32a4a81a62018 (diff) | |
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Stefano Voulaz <s.voulaz@projecktstudio.com> first cut samsung_s3c2450
git-svn-id: svn://svn.berlios.de/openocd/trunk@2556 b42882b7-edfa-0310-969c-e2dbd0fdcd60
-rw-r--r-- | tcl/target/samsung_s3c2450.cfg | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/tcl/target/samsung_s3c2450.cfg b/tcl/target/samsung_s3c2450.cfg new file mode 100644 index 00000000..f7b73930 --- /dev/null +++ b/tcl/target/samsung_s3c2450.cfg @@ -0,0 +1,49 @@ +# Target configuration for the Samsung 2450 system on chip +# Processor : ARM926ejs (wb) rev 0 (v4l) +# Info: JTAG tap: s3c2450.cpu tap/device found: 0x07926F0F + + +# FIX!!! what to use here? +# +# RCLK? +# +# jtag_khz 0 +# +# Really low clock during reset? +# +# jtag_khz 1 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME s3c2450 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a bigendian + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0x07926f0f +} + +#jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xE -irmask 0x0f -expected-id $_CPUTAPID + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs + +# FIX!!!!! should this really use srst_pulls_trst? +# With srst_pulls_trst "reset halt" will not reset into the +# halted mode, but rather "reset run" and then halt the target. +# +# However, without "srst_pulls_trst", then "reset halt" produces weird +# errors: +# WARNING: unknown debug reason: 0x0 +reset_config trst_and_srst
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