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authorDavid Brownell <dbrownell@users.sourceforge.net>2009-11-27 18:50:26 -0800
committerDavid Brownell <dbrownell@users.sourceforge.net>2009-11-27 18:50:26 -0800
commite0cb27df6bc595650ca6ce205803d3aa3218e262 (patch)
tree62a99e2b725a3c90b0e78129721579c818f3db5c
parent4e56a2303b3f68bb647d8bb640a830f7f21ea231 (diff)
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Cortex-A8: support "reset-assert" event
Use the new "reset-assert" event; else SRST; else fail. Tested on an OMAP3, using the event. NOTE: still doesn't handle "reset halt". For some reason neither VCR nor PRCR seemed effective; they held the value that was written, but VCR didn't trigger debug entry when the reset vector fired (maybe the vector needs configuring?) and PRCR refused to hold the chip in reset until deassert() could force the core into debug state. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
-rw-r--r--src/target/cortex_a8.c33
1 files changed, 28 insertions, 5 deletions
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index b85481a9..8402081d 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -1246,6 +1246,21 @@ static int cortex_a8_assert_reset(struct target *target)
LOG_DEBUG(" ");
+ /* FIXME when halt is requested, make it work somehow... */
+
+ /* Issue some kind of warm reset. */
+ if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
+ target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
+ } else if (jtag_get_reset_config() & RESET_HAS_SRST) {
+ /* REVISIT handle "pulls" cases, if there's
+ * hardware that needs them to work.
+ */
+ jtag_add_reset(0, 1);
+ } else {
+ LOG_ERROR("%s: how to reset?", target_name(target));
+ return ERROR_FAIL;
+ }
+
/* registers are now invalid */
register_cache_invalidate(armv7a->armv4_5_common.core_cache);
@@ -1256,14 +1271,22 @@ static int cortex_a8_assert_reset(struct target *target)
static int cortex_a8_deassert_reset(struct target *target)
{
+ int retval;
LOG_DEBUG(" ");
- if (target->reset_halt)
- {
- int retval;
- if ((retval = target_halt(target)) != ERROR_OK)
- return retval;
+ /* be certain SRST is off */
+ jtag_add_reset(0, 0);
+
+ retval = cortex_a8_poll(target);
+
+ if (target->reset_halt) {
+ if (target->state != TARGET_HALTED) {
+ LOG_WARNING("%s: ran after reset and before halt ...",
+ target_name(target));
+ if ((retval = target_halt(target)) != ERROR_OK)
+ return retval;
+ }
}
return ERROR_OK;