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authorzwelch <zwelch@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-06-12 04:14:18 +0000
committerzwelch <zwelch@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-06-12 04:14:18 +0000
commitc6e80f63a3955baed6666e966ab1dd3950ea91b8 (patch)
tree7bd6ae47e80c42ef6699d8043e60108be5a03f32 /src/flash/davinci_nand.c
parenta351c57261d37d73d9e9942063e34e8fe5202380 (diff)
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David Claffey <dnclaffey@gmail.com>:
This patch helps fix MIPS big endian (elf32-tradbigmips) targets. If "-endian big" is not set in target create, the endianess defaults to little. mw and md commands will still work, but binary file loads will have the incorrect word order loaded into memory. The EJTAG processor access data register (PrAcc) is little endian regardless of the CPU endianness; it is always loaded LSB first. This is confirmed by the fact that mips_ejtag_drscan_32() uses buf_set_u32() to load the scan field; buf_set_u32() is a little-endian formatter. For big endian targets, data buffers have to be modified so the LSB of each u32 or u16 is at the lower (first) memory location. If the drscan out_value word order is set using buf_set_u32() then it makes sense to also fixup the in_value with buf_get_u32(); a symmetry argument. This has no affect on little endian hosts. git-svn-id: svn://svn.berlios.de/openocd/trunk@2219 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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