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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-22 03:41:14 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-22 03:41:14 -0800 |
| commit | dd9894f481d127266c201d7075ecbdd34b034124 (patch) | |
| tree | f96d110f7d54368b9435fc9d96018a21c51bfcf0 /src/flash/ocl/at91sam7x/crt.s | |
| parent | ff810723e051ed1f86cffcb565ade6b4d1fc50c8 (diff) | |
| download | openocd_libswd-dd9894f481d127266c201d7075ecbdd34b034124.tar.gz openocd_libswd-dd9894f481d127266c201d7075ecbdd34b034124.tar.bz2 openocd_libswd-dd9894f481d127266c201d7075ecbdd34b034124.tar.xz openocd_libswd-dd9894f481d127266c201d7075ecbdd34b034124.zip | |
ARM: arm_set_cpsr() handles T and J bits
Have arm_set_cpsr() handle the two core state flags, updating
the CPU state. This eliminates code in various debug_entry()
paths, and marginally improves handling of the J bit.
Catch and comment a few holes in the handling of the J bit on
ARM926ejs cores ... it's unlikely our users will care about
Jazelle mode, but we can at least warn of Impending Doom. If
anyone does use it, these breadcrumbs may help them to find
the right path through the code.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/flash/ocl/at91sam7x/crt.s')
0 files changed, 0 insertions, 0 deletions