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authorzwelch <zwelch@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-06-23 22:42:03 +0000
committerzwelch <zwelch@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-06-23 22:42:03 +0000
commit3813fda44adcea486b7308423a699f63d79273ee (patch)
treef515b454cfaea4806d0d307c1d19f1e3081482d1 /src/flash/ocl
parentaea6815462d3302f7f8b6576f59320d5f5985642 (diff)
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- Fixes '==' whitespace
- Replace ')\(==\)\(\w\)' with ') \1 \2'. - Replace '\(\w\)\(==\)\(\w\)' with '\1 \2 \3'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2371 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/flash/ocl')
-rw-r--r--src/flash/ocl/at91sam7x/dcc.c2
-rw-r--r--src/flash/ocl/at91sam7x/samflash.c12
2 files changed, 7 insertions, 7 deletions
diff --git a/src/flash/ocl/at91sam7x/dcc.c b/src/flash/ocl/at91sam7x/dcc.c
index 3507bbe5..a6976595 100644
--- a/src/flash/ocl/at91sam7x/dcc.c
+++ b/src/flash/ocl/at91sam7x/dcc.c
@@ -27,7 +27,7 @@ uint32 dcc_rd(void)
do {
asm volatile ("mrc p14, 0, %0, C0, C0" : "=r" (dcc_reg) : );
- } while ((dcc_reg&1)==0);
+ } while ((dcc_reg&1) == 0);
asm volatile ("mrc p14, 0, %0, C1, C0" : "=r" (dcc_reg) : );
return dcc_reg;
diff --git a/src/flash/ocl/at91sam7x/samflash.c b/src/flash/ocl/at91sam7x/samflash.c
index 893b579f..a534f6d8 100644
--- a/src/flash/ocl/at91sam7x/samflash.c
+++ b/src/flash/ocl/at91sam7x/samflash.c
@@ -86,7 +86,7 @@ int flash_page_program(uint32 *data, int page_num)
else efc_ofs=0;
/* wait until FLASH is ready, just for sure */
- while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
+ while ((inr(MC_FSR+efc_ofs)&MC_FRDY) == 0);
/* calculate page address, only lower 8 bits are used to address the latch,
but the upper part of address is needed for writing to proper EFC */
@@ -103,7 +103,7 @@ int flash_page_program(uint32 *data, int page_num)
outr(MC_FCR+efc_ofs, ((page_num&0x3ff) << 8) | MC_KEY | MC_FCMD_WP);
/* wait until it's done */
- while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
+ while ((inr(MC_FSR+efc_ofs)&MC_FRDY) == 0);
/* check for errors */
if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;
@@ -134,12 +134,12 @@ int flash_erase_plane(int efc_ofs)
if (lockbits&1) {
/* wait until FLASH is ready, just for sure */
- while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
+ while ((inr(MC_FSR+efc_ofs)&MC_FRDY) == 0);
outr(MC_FCR+efc_ofs, ((page_num&0x3ff) << 8) | 0x5a000004);
/* wait until it's done */
- while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
+ while ((inr(MC_FSR+efc_ofs)&MC_FRDY) == 0);
/* check for errors */
if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;
@@ -151,13 +151,13 @@ int flash_erase_plane(int efc_ofs)
}
/* wait until FLASH is ready, just for sure */
- while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
+ while ((inr(MC_FSR+efc_ofs)&MC_FRDY) == 0);
/* erase all command to FCR */
outr(MC_FCR+efc_ofs, 0x5a000008);
/* wait until it's done */
- while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
+ while ((inr(MC_FSR+efc_ofs)&MC_FRDY) == 0);
/* check for errors */
if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;