diff options
author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-13 13:44:50 -0800 |
---|---|---|
committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-13 13:44:50 -0800 |
commit | 38e8d60f79fd51424c556e07653713254c2d9b4e (patch) | |
tree | ec0b8cea908e83bd369f59024e96e0c73d0469a2 /src/flash/ocl | |
parent | afe0298399bd06700926822e6d49c5bc44151956 (diff) | |
download | openocd_libswd-38e8d60f79fd51424c556e07653713254c2d9b4e.tar.gz openocd_libswd-38e8d60f79fd51424c556e07653713254c2d9b4e.tar.bz2 openocd_libswd-38e8d60f79fd51424c556e07653713254c2d9b4e.tar.xz openocd_libswd-38e8d60f79fd51424c556e07653713254c2d9b4e.zip |
target.cfg: label ETBs correctly
Various cores with an ETB have its TAP misnamed ... either as a
boundary scan TAP or as the iMX "Secure JTAG Controller" (which
is, among other things, a JRC that could be used to shorten
scan chains).
Use the correct name for these TAPs, which we can recognize since
their IDs were assigned by ARM and these chips all document the
presence of an ETB. The 0x2b900f0f is ETB11; the 0x1b900f0f
is an older module, just called "ETB".
Also shrink the ETB's IR configuration; the default IR-Capture
value is fine, and the mask can specify that all four bits are
safe to check (per ARM documentation).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/flash/ocl')
0 files changed, 0 insertions, 0 deletions