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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-12 20:24:41 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-12 20:24:41 -0800 |
| commit | d47764ff7176b6e3d97b49e82d4db7fe17c8e552 (patch) | |
| tree | c8f1c14a6041a4a70f546afa1047b7633a73476d /src/flash/s3c2412_nand.c | |
| parent | 26849ad60d269b0e8d254882bc75268a393dd2a1 (diff) | |
| download | openocd_libswd-d47764ff7176b6e3d97b49e82d4db7fe17c8e552.tar.gz openocd_libswd-d47764ff7176b6e3d97b49e82d4db7fe17c8e552.tar.bz2 openocd_libswd-d47764ff7176b6e3d97b49e82d4db7fe17c8e552.tar.xz openocd_libswd-d47764ff7176b6e3d97b49e82d4db7fe17c8e552.zip | |
ETM: start support for ETMv2+
ARM11 and newer cores include updated ETM modules. Recognize
their version codes and some key config differences. Sanity
checked on an OMAP2, with an ETM11RV r0p1 (ETMv3.1).
This still handles only scan chain 6, with at most 128 registers.
Newer cores (mostly, Cortex) will need to use the DAP instead.
Note that the newer ETM modules don't quite fit the quirky config
model of the older ones ... having more port widths is easy, but
the modes aren't the same. That still needs to change.
Fix a curious bug ... how did the register cache NOT get saved??
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/flash/s3c2412_nand.c')
0 files changed, 0 insertions, 0 deletions