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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-09 06:28:49 +0000 |
|---|---|---|
| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-09 06:28:49 +0000 |
| commit | aa46b1537792688510717cbbc215da160c2cb665 (patch) | |
| tree | 86a902ae1c0e568e0793c84c05643aaecbab8801 /src/flash | |
| parent | 8b2b0071a9a1f412a752da21542d4bcdaccd5751 (diff) | |
| download | openocd_libswd-aa46b1537792688510717cbbc215da160c2cb665.tar.gz openocd_libswd-aa46b1537792688510717cbbc215da160c2cb665.tar.bz2 openocd_libswd-aa46b1537792688510717cbbc215da160c2cb665.tar.xz openocd_libswd-aa46b1537792688510717cbbc215da160c2cb665.zip | |
David Brownell <david-b@pacbell.net>
Optionally shave time off the armv4_5 run_algorithm() code: let
them terminate using software breakpoints, avoiding roundtrips
to manage hardware ones.
Enable this by using BKPT to terminate execution instead of "branch
to here" loops. Then pass zero as the exit address, except when
running on an ARMv4 core. ARM7TDMI, ARM9TDMI, and derived cores
now set a flag saying they're ARMv4.
Use that mechanism in arm_nandwrite(), for about 3% speedup on a
DaVinci ARM926 core; not huge, but it helps. Some other algorithms
could use this too (mostly flavors of flash operation).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2680 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/flash')
| -rw-r--r-- | src/flash/arm_nandio.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/flash/arm_nandio.c b/src/flash/arm_nandio.c index fb501e56..8087221a 100644 --- a/src/flash/arm_nandio.c +++ b/src/flash/arm_nandio.c @@ -33,7 +33,6 @@ * For now this only supports ARMv4 and ARMv5 cores. * * Enhancements to target_run_algorithm() could enable: - * - faster writes: on ARMv5+ don't setup/teardown hardware breakpoint * - ARMv6 and ARMv7 cores in ARM mode * * Different code fragments could handle: @@ -44,8 +43,10 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size) { target_t *target = nand->target; armv4_5_algorithm_t algo; + armv4_5_common_t *armv4_5 = target->arch_info; reg_param_t reg_params[3]; uint32_t target_buf; + uint32_t exit = 0; int retval; /* Inputs: @@ -112,11 +113,13 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size) buf_set_u32(reg_params[1].value, 0, 32, target_buf); buf_set_u32(reg_params[2].value, 0, 32, size); + /* armv4 must exit using a hardware breakpoint */ + if (armv4_5->is_armv4) + exit = nand->copy_area->address + sizeof(code) - 4; + /* use alg to write data from work area to NAND chip */ retval = target_run_algorithm(target, 0, NULL, 3, reg_params, - nand->copy_area->address, - nand->copy_area->address + sizeof(code) - 4, - 1000, &algo); + nand->copy_area->address, exit, 1000, &algo); if (retval != ERROR_OK) LOG_ERROR("error executing hosted NAND write"); |