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| author | Øyvind Harboe <oyvind.harboe@zylin.com> | 2010-07-16 10:51:14 +0200 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2010-07-16 12:18:35 +0200 |
| commit | bb588bdaec2acb6898c1f86f674b829ee2098642 (patch) | |
| tree | 69ba2224f8616b483b41f52bfcb9ef142a99bd8f /src/jtag/zy1000 | |
| parent | 0672a6497ec1ea59905487c01a65ffad79449538 (diff) | |
| download | openocd_libswd-bb588bdaec2acb6898c1f86f674b829ee2098642.tar.gz openocd_libswd-bb588bdaec2acb6898c1f86f674b829ee2098642.tar.bz2 openocd_libswd-bb588bdaec2acb6898c1f86f674b829ee2098642.tar.xz openocd_libswd-bb588bdaec2acb6898c1f86f674b829ee2098642.zip | |
debug feature: jtagtcpip, improved performance
only check error flag when rclk is actually enabled.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Diffstat (limited to 'src/jtag/zy1000')
| -rw-r--r-- | src/jtag/zy1000/zy1000.c | 31 |
1 files changed, 22 insertions, 9 deletions
diff --git a/src/jtag/zy1000/zy1000.c b/src/jtag/zy1000/zy1000.c index 013d8658..a1104ef4 100644 --- a/src/jtag/zy1000/zy1000.c +++ b/src/jtag/zy1000/zy1000.c @@ -72,6 +72,10 @@ #endif + +/* The software needs to check if it's in RCLK mode or not */ +static bool zy1000_rclk = false; + static int zy1000_khz(int khz, int *jtag_speed) { if (khz == 0) @@ -222,11 +226,13 @@ int zy1000_speed(int speed) /* flush JTAG master FIFO before setting speed */ waitIdle(); + zy1000_rclk = false; + if (speed == 0) { /*0 means RCLK*/ - speed = 0; ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x100); + zy1000_rclk = true; LOG_DEBUG("jtag_speed using RCLK"); } else @@ -456,17 +462,24 @@ int interface_jtag_execute_queue(void) uint32_t empty; waitIdle(); - ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, empty); - /* clear JTAG error register */ - ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x400); - if ((empty&0x400) != 0) + if (zy1000_rclk) { - LOG_WARNING("RCLK timeout"); - /* the error is informative only as we don't want to break the firmware if there - * is a false positive. + /* Only check for errors when using RCLK to speed up + * jtag over TCP/IP */ -// return ERROR_FAIL; + ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, empty); + /* clear JTAG error register */ + ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x400); + + if ((empty&0x400) != 0) + { + LOG_WARNING("RCLK timeout"); + /* the error is informative only as we don't want to break the firmware if there + * is a false positive. + */ + // return ERROR_FAIL; + } } return ERROR_OK; } |