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authoroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2008-03-04 06:46:44 +0000
committeroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2008-03-04 06:46:44 +0000
commit58cccae6396b9279852c4eb06bc04b690561e3bb (patch)
treedef35703893dd1cb55363e4ca3e19715f8d56527 /src/target/arm11.h
parent5c2b85dfecb107b31799f736dfcfeb4d96bd6ed6 (diff)
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Michael Bruck:
- Added simulate_reset_on_next_halt that can be extended to do all sorts of cleanups for systems without proper reset. Right now it just writes 0 to the control register to disable caches. - Step skips over Wait for Interrupt instruction - fix for count - fix for printf format errors git-svn-id: svn://svn.berlios.de/openocd/trunk@439 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/arm11.h')
-rw-r--r--src/target/arm11.h13
1 files changed, 8 insertions, 5 deletions
diff --git a/src/target/arm11.h b/src/target/arm11.h
index 0b203325..638c2ca9 100644
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -16,6 +16,7 @@
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
+
#ifndef ARM11_H
#define ARM11_H
@@ -23,12 +24,13 @@
#include "register.h"
#include "embeddedice.h"
#include "arm_jtag.h"
+#include <stdbool.h>
#define asizeof(x) (sizeof(x) / sizeof((x)[0]))
-#define NEW(type, variable, items) \
- type * variable = malloc(sizeof(type) * items)
+#define NEW(type, variable, items) \
+ type * variable = calloc(1, sizeof(type) * items)
#define ARM11_REGCACHE_MODEREGS 0
@@ -77,8 +79,9 @@ typedef struct arm11_common_s
u32 last_dscr; /**< Last retrieved DSCR value;
* Can be used to detect changes */
- u8 trst_active;
- u8 halt_requested;
+ bool trst_active;
+ bool halt_requested;
+ bool simulate_reset_on_next_halt;
/** \name Shadow registers to save processor state */
/*@{*/
@@ -254,7 +257,7 @@ int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state st
*/
typedef struct arm11_sc7_action_s
{
- int write; /**< Access mode: true for write, false for read. */
+ bool write; /**< Access mode: true for write, false for read. */
u8 address; /**< Register address mode. Use enum #arm11_sc7 */
u32 value; /**< If write then set this to value to be written.
In read mode this receives the read value when the