Transform 'u32' to 'uint32_t' in src/target/arm*

- Replace '\([^_]\)u32' with '\1uint32_t'.
- Replace '^u32' with 'uint32_t'.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2278 b42882b7-edfa-0310-969c-e2dbd0fdcd60

1 files changed, 39 insertions, 39 deletions

diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 8fe2cc40..6e4e076f 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -48,8 +48,8 @@ int arm920t_target_create(struct target_s *target, Jim_Interp *interp);
 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 int arm920t_quit(void);
 int arm920t_arch_state(struct target_s *target);
-int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
-int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
+int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 int arm920t_soft_reset_halt(struct target_s *target);
 
 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
@@ -93,7 +93,7 @@ target_type_t arm920t_target =
 	.quit = arm920t_quit
 };
 
-int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
+int arm920t_read_cp15_physical(target_t *target, int reg_addr, uint32_t *value)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -143,7 +143,7 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
 	return ERROR_OK;
 }
 
-int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
+int arm920t_write_cp15_physical(target_t *target, int reg_addr, uint32_t value)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -189,7 +189,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
 	return ERROR_OK;
 }
 
-int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
+int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, uint32_t arm_opcode)
 {
 	int retval;
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -244,12 +244,12 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
 	return ERROR_OK;
 }
 
-int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address, u32 *value)
+int arm920t_read_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t address, uint32_t *value)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
-	u32* regs_p[1];
-	u32 regs[2];
-	u32 cp15c15 = 0x0;
+	uint32_t* regs_p[1];
+	uint32_t regs[2];
+	uint32_t cp15c15 = 0x0;
 
 	/* load address into R1 */
 	regs[1] = address;
@@ -287,11 +287,11 @@ int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address
 	return ERROR_OK;
 }
 
-int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value, u32 address)
+int arm920t_write_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t value, uint32_t address)
 {
-	u32 cp15c15 = 0x0;
+	uint32_t cp15c15 = 0x0;
 	armv4_5_common_t *armv4_5 = target->arch_info;
-	u32 regs[2];
+	uint32_t regs[2];
 
 	/* load value, address into R0, R1 */
 	regs[0] = value;
@@ -325,10 +325,10 @@ int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value,
 	return ERROR_OK;
 }
 
-u32 arm920t_get_ttb(target_t *target)
+uint32_t arm920t_get_ttb(target_t *target)
 {
 	int retval;
-	u32 ttb = 0x0;
+	uint32_t ttb = 0x0;
 
 	if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
 		return retval;
@@ -338,7 +338,7 @@ u32 arm920t_get_ttb(target_t *target)
 
 void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 {
-	u32 cp15_control;
+	uint32_t cp15_control;
 
 	/* read cp15 control register */
 	arm920t_read_cp15_physical(target, 0x2, &cp15_control);
@@ -358,7 +358,7 @@ void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_
 
 void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 {
-	u32 cp15_control;
+	uint32_t cp15_control;
 
 	/* read cp15 control register */
 	arm920t_read_cp15_physical(target, 0x2, &cp15_control);
@@ -378,7 +378,7 @@ void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_c
 
 void arm920t_post_debug_entry(target_t *target)
 {
-	u32 cp15c15;
+	uint32_t cp15c15;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
@@ -391,7 +391,7 @@ void arm920t_post_debug_entry(target_t *target)
 
 	if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
 	{
-		u32 cache_type_reg;
+		uint32_t cache_type_reg;
 		/* identify caches */
 		arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
 		jtag_execute_queue();
@@ -424,7 +424,7 @@ void arm920t_post_debug_entry(target_t *target)
 
 void arm920t_pre_restore_context(target_t *target)
 {
-	u32 cp15c15;
+	uint32_t cp15c15;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
@@ -518,7 +518,7 @@ int arm920t_arch_state(struct target_s *target)
 	return ERROR_OK;
 }
 
-int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
+int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	int retval;
 
@@ -527,7 +527,7 @@ int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 coun
 	return retval;
 }
 
-int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
+int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	int retval;
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -543,7 +543,7 @@ int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 cou
 		if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 		{
 			LOG_DEBUG("D-Cache enabled, writing through to main memory");
-			u32 pa, cb, ap;
+			uint32_t pa, cb, ap;
 			int type, domain;
 
 			pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap);
@@ -731,11 +731,11 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
 	arm9tdmi_common_t *arm9tdmi;
 	arm920t_common_t *arm920t;
 	arm_jtag_t *jtag_info;
-	u32 cp15c15;
-	u32 cp15_ctrl, cp15_ctrl_saved;
-	u32 regs[16];
-	u32 *regs_p[16];
-	u32 C15_C_D_Ind, C15_C_I_Ind;
+	uint32_t cp15c15;
+	uint32_t cp15_ctrl, cp15_ctrl_saved;
+	uint32_t regs[16];
+	uint32_t *regs_p[16];
+	uint32_t C15_C_D_Ind, C15_C_I_Ind;
 	int i;
 	FILE *output;
 	arm920t_cache_line_t d_cache[8][64], i_cache[8][64];
@@ -983,13 +983,13 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 	arm9tdmi_common_t *arm9tdmi;
 	arm920t_common_t *arm920t;
 	arm_jtag_t *jtag_info;
-	u32 cp15c15;
-	u32 cp15_ctrl, cp15_ctrl_saved;
-	u32 regs[16];
-	u32 *regs_p[16];
+	uint32_t cp15c15;
+	uint32_t cp15_ctrl, cp15_ctrl_saved;
+	uint32_t regs[16];
+	uint32_t *regs_p[16];
 	int i;
 	FILE *output;
-	u32 Dlockdown, Ilockdown;
+	uint32_t Dlockdown, Ilockdown;
 	arm920t_tlb_entry_t d_tlb[64], i_tlb[64];
 	int victim;
 
@@ -1293,7 +1293,7 @@ int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
 
 		if (argc == 1)
 		{
-			u32 value;
+			uint32_t value;
 			if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
 			{
 				command_print(cmd_ctx, "couldn't access reg %i", address);
@@ -1308,7 +1308,7 @@ int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
 		}
 		else if (argc == 2)
 		{
-			u32 value = strtoul(args[1], NULL, 0);
+			uint32_t value = strtoul(args[1], NULL, 0);
 			if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
 			{
 				command_print(cmd_ctx, "couldn't access reg %i", address);
@@ -1348,11 +1348,11 @@ int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, c
 	/* one or more argument, access a single register (write if second argument is given */
 	if (argc >= 1)
 	{
-		u32 opcode = strtoul(args[0], NULL, 0);
+		uint32_t opcode = strtoul(args[0], NULL, 0);
 
 		if (argc == 1)
 		{
-			u32 value;
+			uint32_t value;
 			if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
 			{
 				command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
@@ -1363,7 +1363,7 @@ int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, c
 		}
 		else if (argc == 2)
 		{
-			u32 value = strtoul(args[1], NULL, 0);
+			uint32_t value = strtoul(args[1], NULL, 0);
 			if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
 			{
 				command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
@@ -1373,8 +1373,8 @@ int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, c
 		}
 		else if (argc == 3)
 		{
-			u32 value = strtoul(args[1], NULL, 0);
-			u32 address = strtoul(args[2], NULL, 0);
+			uint32_t value = strtoul(args[1], NULL, 0);
+			uint32_t address = strtoul(args[2], NULL, 0);
 			if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
 			{
 				command_print(cmd_ctx, "couldn't execute %8.8x", opcode);