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| author | ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-07-21 20:03:17 +0000 |
|---|---|---|
| committer | ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-07-21 20:03:17 +0000 |
| commit | cd0ca916b342215e5bde80586051cb105fedad56 (patch) | |
| tree | 4218f89bcf25c3ecac803cba1a971228f60f2d3e /src/target/armv7m.c | |
| parent | 55b1ea1d8e4558e68a58f33a9900163605f8333f (diff) | |
| download | openocd_libswd-cd0ca916b342215e5bde80586051cb105fedad56.tar.gz openocd_libswd-cd0ca916b342215e5bde80586051cb105fedad56.tar.bz2 openocd_libswd-cd0ca916b342215e5bde80586051cb105fedad56.tar.xz openocd_libswd-cd0ca916b342215e5bde80586051cb105fedad56.zip | |
David Brownell <david-b@pacbell.net>:
Revert parts of the previous ARMv7-M register patch.
It turns out that part of the issue is a documentation
problem for the Cortex-M3 r1 parts. So for the rest,
simpler fixes are possible (in followup patch).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2552 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/armv7m.c')
| -rw-r--r-- | src/target/armv7m.c | 31 |
1 files changed, 11 insertions, 20 deletions
diff --git a/src/target/armv7m.c b/src/target/armv7m.c index 02a664aa..58494430 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -60,8 +60,8 @@ char* armv7m_core_reg_list[] = "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", "xPSR", "msp", "psp", - /* reg 20 has 4 bytes: CONTROL, FAULTMASK, BASEPRI, PRIMASK */ - "spec20", + /* Registers accessed through special reg 20 */ + "primask", "basepri", "faultmask", "control" }; uint8_t armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; @@ -111,11 +111,11 @@ armv7m_core_reg_t armv7m_core_reg_list_arch_info[] = {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */ {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */ - /* FIXME the register numbers here are core-specific. - * Numbers 0..18 above work for all Cortex-M3 revisions. - * Number 20 below works for CM3 r2p0 and later. - */ - {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, + /* CORE_SP are accesible using coreregister 20 */ + {19, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */ + {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */ + {21, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */ + {22, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL} /* CONTROL */ }; int armv7m_core_reg_arch_type = -1; @@ -387,21 +387,12 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ armv7m_set_core_reg(reg, reg_params[i].value); } - /* NOTE: CONTROL is bits 31:24 of SPEC20 register, if it's present; - * holding a two-bit field. - * - * FIXME need a solution using ARMV7M_T_MSR(). Use it at least for - * earlier cores. - */ - if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY - && armv7m->has_spec20) + if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY) { LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode); - - buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_SPEC20].value, - 24, 2, armv7m_algorithm_info->core_mode); - armv7m->core_cache->reg_list[ARMV7M_SPEC20].dirty = 1; - armv7m->core_cache->reg_list[ARMV7M_SPEC20].valid = 1; + buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode); + armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1; + armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1; } /* ARMV7M always runs in Thumb state */ |