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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-04 05:20:45 +0000 |
|---|---|---|
| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-04 05:20:45 +0000 |
| commit | 51be978b4329008ece5a501563ffcc4059baef8f (patch) | |
| tree | b0206921c6843aafcc70b6a071d66290789fd716 /src/target/cortex_a8.c | |
| parent | ce89c7bf6588c7b2800c4ca453278b6f94795130 (diff) | |
| download | openocd_libswd-51be978b4329008ece5a501563ffcc4059baef8f.tar.gz openocd_libswd-51be978b4329008ece5a501563ffcc4059baef8f.tar.bz2 openocd_libswd-51be978b4329008ece5a501563ffcc4059baef8f.tar.xz openocd_libswd-51be978b4329008ece5a501563ffcc4059baef8f.zip | |
Matt Hsu <matt@0xlab.org> Tidy up the bit-offset operation for DSCR register
git-svn-id: svn://svn.berlios.de/openocd/trunk@2666 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/cortex_a8.c')
| -rw-r--r-- | src/target/cortex_a8.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index 829bf3dc..a806669d 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -166,7 +166,7 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode) retvalue = mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr); } - while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */ + while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */ mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode); @@ -175,7 +175,7 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode) retvalue = mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr); } - while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */ + while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */ return retvalue; } @@ -291,7 +291,7 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target, retval = mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr); } - while ((dscr & (1 << 29)) == 0); /* Wait for DTRRXfull */ + while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0); /* Wait for DTRRXfull */ retval = mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value); @@ -436,7 +436,7 @@ int cortex_a8_halt(target_t *target) do { mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr); - } while ((dscr & (1 << 0)) == 0); + } while ((dscr & (1 << DSCR_CORE_HALTED)) == 0); target->debug_reason = DBG_REASON_DBGRQ; @@ -535,7 +535,7 @@ int cortex_a8_resume(struct target_s *target, int current, do { mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr); - } while ((dscr & (1 << 1)) == 0); + } while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0); target->debug_reason = DBG_REASON_NOTHALTED; target->state = TARGET_RUNNING; @@ -582,7 +582,7 @@ int cortex_a8_debug_entry(target_t *target) /* Enable the ITR execution once we are in debug mode */ mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr); - dscr |= (1 << 13); + dscr |= (1 << DSCR_EXT_INT_EN); retval = mem_ap_write_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr); |