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| author | dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-21 18:40:55 +0000 |
|---|---|---|
| committer | dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-21 18:40:55 +0000 |
| commit | 86a7d813a165fda2816b8152342219b6c4ae2fc4 (patch) | |
| tree | 283daa370b600184a025a9b1188be36994ba6eb6 /src/target/cortex_a8.c | |
| parent | 0bcf5a6b76ad1cb4d871733f438e2a261bb88e12 (diff) | |
| download | openocd_libswd-86a7d813a165fda2816b8152342219b6c4ae2fc4.tar.gz openocd_libswd-86a7d813a165fda2816b8152342219b6c4ae2fc4.tar.bz2 openocd_libswd-86a7d813a165fda2816b8152342219b6c4ae2fc4.tar.xz openocd_libswd-86a7d813a165fda2816b8152342219b6c4ae2fc4.zip | |
Remove annoying end-of-line whitespace from most src/*
files; omitted src/httpd
git-svn-id: svn://svn.berlios.de/openocd/trunk@2742 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/cortex_a8.c')
| -rw-r--r-- | src/target/cortex_a8.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index 46e2e717..f6f13cfc 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -138,8 +138,8 @@ int cortex_a8_init_debug_access(target_t *target) /* Clear Sticky Power Down status Bit in PRSR to enable access to the registers in the Core Power Domain */ retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy); - /* Enabling of instruction execution in debug mode is done in debug_entry code */ - + /* Enabling of instruction execution in debug mode is done in debug_entry code */ + return retval; } @@ -1374,7 +1374,7 @@ int cortex_a8_examine(struct target_s *target) uint32_t didr, ctypr, ttypr, cpuid; LOG_DEBUG("TODO"); - + /* Here we shall insert a proper ROM Table scan */ armv7a->debug_base = OMAP3530_DEBUG_BASE; @@ -1451,7 +1451,7 @@ int cortex_a8_examine(struct target_s *target) /* Configure core debug access */ cortex_a8_init_debug_access(target); - + target->type->examined = 1; return retval; |