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author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-22 10:19:58 -0800 |
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committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-22 10:27:29 -0800 |
commit | ab5ac33fd462c37e4cf5a6bc1fe5fd0631e44469 (patch) | |
tree | 84c1fcc02b2030c7b60fed0c2b39399dcc07c14f /src/target/cortex_a8.c | |
parent | 5416c525d4e232161572fbbd1b200a7f3a7c2819 (diff) | |
download | openocd_libswd-ab5ac33fd462c37e4cf5a6bc1fe5fd0631e44469.tar.gz openocd_libswd-ab5ac33fd462c37e4cf5a6bc1fe5fd0631e44469.tar.bz2 openocd_libswd-ab5ac33fd462c37e4cf5a6bc1fe5fd0631e44469.tar.xz openocd_libswd-ab5ac33fd462c37e4cf5a6bc1fe5fd0631e44469.zip |
ARM: remove 'armv4_5_common_s' migration #define
Finish migrating from the old symbol to the new one.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/cortex_a8.c')
-rw-r--r-- | src/target/cortex_a8.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index fa26b6ab..de579feb 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -457,7 +457,7 @@ static int cortex_a8_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common; + struct arm *armv4_5 = &armv7a->armv4_5_common; struct swjdp_common *swjdp = &armv7a->swjdp_info; // struct breakpoint *breakpoint = NULL; @@ -587,7 +587,7 @@ static int cortex_a8_debug_entry(struct target *target) struct working_area *regfile_working_area = NULL; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = target_to_armv7a(target); - struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common; + struct arm *armv4_5 = &armv7a->armv4_5_common; struct swjdp_common *swjdp = &armv7a->swjdp_info; struct reg *reg; @@ -743,7 +743,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address, int handle_breakpoints) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common; + struct arm *armv4_5 = &armv7a->armv4_5_common; struct breakpoint *breakpoint = NULL; struct breakpoint stepbreakpoint; @@ -915,7 +915,7 @@ static int cortex_a8_load_core_reg_u32(struct target *target, int num, armv4_5_mode_t mode, uint32_t * value) { int retval; - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_armv4_5(target); if ((num <= ARM_CPSR)) { @@ -953,7 +953,7 @@ static int cortex_a8_store_core_reg_u32(struct target *target, int num, { int retval; // uint32_t reg; - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_armv4_5(target); #ifdef ARMV7_GDB_HACKS /* If the LR register is being modified, make sure it will put us @@ -998,7 +998,7 @@ static int cortex_a8_read_core_reg(struct target *target, struct reg *r, { uint32_t value; int retval; - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_armv4_5(target); struct reg *cpsr_r = NULL; uint32_t cpsr = 0; unsigned cookie = num; @@ -1053,7 +1053,7 @@ static int cortex_a8_write_core_reg(struct target *target, struct reg *r, int num, enum armv4_5_mode mode, uint32_t value) { int retval; - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_armv4_5(target); struct reg *cpsr_r = NULL; uint32_t cpsr = 0; unsigned cookie = num; @@ -1584,7 +1584,7 @@ static int cortex_a8_examine(struct target *target) static void cortex_a8_build_reg_cache(struct target *target) { struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_armv4_5(target); armv4_5->core_type = ARM_MODE_MON; |