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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-18 13:22:27 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-18 13:22:27 -0800 |
| commit | bbebfd9e134ec84a29dd68bc3661ead57435a4c3 (patch) | |
| tree | db209d49fd8d9c6f41e104d1b1af7c19419584c6 /src/target/cortex_a8.c | |
| parent | 9b1f9810b090958bb4a669034173a01683c6e3e9 (diff) | |
| download | openocd_libswd-bbebfd9e134ec84a29dd68bc3661ead57435a4c3.tar.gz openocd_libswd-bbebfd9e134ec84a29dd68bc3661ead57435a4c3.tar.bz2 openocd_libswd-bbebfd9e134ec84a29dd68bc3661ead57435a4c3.tar.xz openocd_libswd-bbebfd9e134ec84a29dd68bc3661ead57435a4c3.zip | |
ARM: add "core_type" field to "struct arm"
It's used to flag cores with the "TrustZone" extension,
and is used in subsequent patches to set up support for
the registers shadowed by its new secure monitor mode.
The ARM1176 and Cortex-A8 both support this new mode.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/cortex_a8.c')
| -rw-r--r-- | src/target/cortex_a8.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index 04b3f872..f8ff3920 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -1423,6 +1423,8 @@ static void cortex_a8_build_reg_cache(struct target *target) struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + armv4_5->core_type = ARM_MODE_MON; + (*cache_p) = armv4_5_build_reg_cache(target, armv4_5); armv4_5->core_cache = (*cache_p); } |