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| author | ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-08-18 19:55:01 +0000 |
|---|---|---|
| committer | ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-08-18 19:55:01 +0000 |
| commit | 69dd81dcf807afebdbf9644bf2baf023de373f25 (patch) | |
| tree | 44764c27741ac101047929ffc7e60317a3e98c51 /src/target/cortex_m3.c | |
| parent | 1b092a27f0d94cb5e2e9aa53552aaf5c71146260 (diff) | |
| download | openocd_libswd-69dd81dcf807afebdbf9644bf2baf023de373f25.tar.gz openocd_libswd-69dd81dcf807afebdbf9644bf2baf023de373f25.tar.bz2 openocd_libswd-69dd81dcf807afebdbf9644bf2baf023de373f25.tar.xz openocd_libswd-69dd81dcf807afebdbf9644bf2baf023de373f25.zip | |
David Brownell [david-b@pacbell.net]:
Simplify dumping of register lists by only printing cached values
if they are marked as valid. Most of the time, they are invalid;
so printing *any* value is just misleading.
Note that for ARM7 and ARM9 most EmbeddedICE registers (except for
debug status) could be cached most of the time; and their register
cache isn't maintained properly (many accesses seem to bypass that
cache code).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2594 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/cortex_m3.c')
0 files changed, 0 insertions, 0 deletions