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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-04-02 14:47:21 +0000 |
|---|---|---|
| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-04-02 14:47:21 +0000 |
| commit | 349f62f74fdc1278efd00a0e6301e1a0199cc128 (patch) | |
| tree | 8c45f0e6d519e75e21a3cc65ca8f75fd52e347bb /src/target/event | |
| parent | 6549d376e49a3dd4071a6cb4420bbba8f1ecf9c5 (diff) | |
| download | openocd_libswd-349f62f74fdc1278efd00a0e6301e1a0199cc128.tar.gz openocd_libswd-349f62f74fdc1278efd00a0e6301e1a0199cc128.tar.bz2 openocd_libswd-349f62f74fdc1278efd00a0e6301e1a0199cc128.tar.xz openocd_libswd-349f62f74fdc1278efd00a0e6301e1a0199cc128.zip | |
Edgar Grimberg sharpened the str912 target script.
git-svn-id: svn://svn.berlios.de/openocd/trunk@535 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/event')
| -rw-r--r-- | src/target/event/str912_program.script | 9 | ||||
| -rw-r--r-- | src/target/event/str912_reset.script | 21 |
2 files changed, 21 insertions, 9 deletions
diff --git a/src/target/event/str912_program.script b/src/target/event/str912_program.script deleted file mode 100644 index df0239b9..00000000 --- a/src/target/event/str912_program.script +++ /dev/null @@ -1,9 +0,0 @@ -str9x flash_config 0 4 2 0 0x80000 -flash protect 0 0 7 off - - - - - - - diff --git a/src/target/event/str912_reset.script b/src/target/event/str912_reset.script new file mode 100644 index 00000000..8178c82c --- /dev/null +++ b/src/target/event/str912_reset.script @@ -0,0 +1,21 @@ +mww 0xFFFFFD44, 0x00008000 #Disable watchdog
+mww 0xFFFFFC20, 0x00000601 #Enable Main oscillator
+sleep 20
+mww 0xFFFFFC30, 0x00000001 #Switch master clock to CPU clock, write 1 to PMC_MCKR
+sleep 20
+
+
+# -- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000,
+# when the bank 0 is the boot bank, then enable the Bank 1. */
+
+mww 0x54000000, 0x4 #BOOT BANK Size = (2^4) * 32 = 512KB
+mww 0x54000004, 0x2 #NON BOOT BANK Size = (2^2) * 8 = 32KB
+mww 0x5400000C, 0x0 #BOOT BANK Address = 0x0
+mww 0x54000010, 0x20000 #NON BOOT BANK Address = 0x80000
+mww 0x54000018, 0x18 #Enable CS on both banks
+
+# -- Enable 96K RAM */
+mww 0x5C002034, 0x0191 # PFQBC enabled / DTCM & AHB wait-states disabled
+arm966e cp15 15, 0x60000 #Set bits 17-18 (DTCM/ITCM order bits) of the Core Configuration Control Register
+
+flash protect 0 0 7 off
|