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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-10-14 06:21:17 +0000 |
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| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-10-14 06:21:17 +0000 |
| commit | 539527ab74f73bfd27d055d7ca20d30176be5e17 (patch) | |
| tree | 0cbc6b696813a313807a63f3d0810d760ac339b4 /src/target/mips_ejtag.c | |
| parent | 3600e7c6e04117b192e428adb7ff7d9515c982f5 (diff) | |
| download | openocd_libswd-539527ab74f73bfd27d055d7ca20d30176be5e17.tar.gz openocd_libswd-539527ab74f73bfd27d055d7ca20d30176be5e17.tar.bz2 openocd_libswd-539527ab74f73bfd27d055d7ca20d30176be5e17.tar.xz openocd_libswd-539527ab74f73bfd27d055d7ca20d30176be5e17.zip | |
John McCarthy <jgmcc@magma.ca> cleans up the usage of the
ejtag_info->ejtag_ctrl variable. It was being overwritten by the value read back from the EJTAG CONTROL register. Because of the way this register works you do not want to use the value returned to write the register, you always want to write the bits explicitly.
The second patch just reduces the DMA retries to 0 in anticipation of removing the retry code altogether.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1049 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/mips_ejtag.c')
| -rw-r--r-- | src/target/mips_ejtag.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c index 6e6bd934..09470b08 100644 --- a/src/target/mips_ejtag.c +++ b/src/target/mips_ejtag.c @@ -194,18 +194,19 @@ int mips_ejtag_config_step(mips_ejtag_t *ejtag_info, int enable_step) int mips_ejtag_enter_debug(mips_ejtag_t *ejtag_info) { + u32 ejtag_ctrl; jtag_add_end_state(TAP_RTI); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); /* set debug break bit */ - ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV | EJTAG_CTRL_JTAGBRK; - mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl); + ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK; + mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); /* break bit will be cleared by hardware */ - ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV; - mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl); - LOG_DEBUG("ejtag_ctrl: 0x%8.8x", ejtag_info->ejtag_ctrl); - if((ejtag_info->ejtag_ctrl & EJTAG_CTRL_BRKST) == 0) + ejtag_ctrl = ejtag_info->ejtag_ctrl; + mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); + LOG_DEBUG("ejtag_ctrl: 0x%8.8x", ejtag_ctrl); + if((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0) LOG_DEBUG("Failed to enter Debug Mode!"); return ERROR_OK; |