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| author | ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-11-13 21:40:26 +0000 |
|---|---|---|
| committer | ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-11-13 21:40:26 +0000 |
| commit | c0787b699496080d48174713a0b30e81ef5db3be (patch) | |
| tree | 9dab9d70f9d87a6505592ae5484dfe0686d3ccbe /src/target/mips_ejtag.c | |
| parent | 368daf44ff6aecb522952872a44bcf9e26b836f3 (diff) | |
| download | openocd_libswd-c0787b699496080d48174713a0b30e81ef5db3be.tar.gz openocd_libswd-c0787b699496080d48174713a0b30e81ef5db3be.tar.bz2 openocd_libswd-c0787b699496080d48174713a0b30e81ef5db3be.tar.xz openocd_libswd-c0787b699496080d48174713a0b30e81ef5db3be.zip | |
- correct the register hi/lo read - wrong way round
- all the register now can be written to, including the special CP0 regs.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1169 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/mips_ejtag.c')
| -rw-r--r-- | src/target/mips_ejtag.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c index 09470b08..c169c6f0 100644 --- a/src/target/mips_ejtag.c +++ b/src/target/mips_ejtag.c @@ -164,8 +164,8 @@ int mips_ejtag_step_disable(mips_ejtag_t *ejtag_info) MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(1,0,15), /* sw $2,($15) */ - MIPS32_SW(2,0,15), /* sw $3,($15) */ + MIPS32_SW(1,0,15), /* sw $1,($15) */ + MIPS32_SW(2,0,15), /* sw $2,($15) */ MIPS32_MFC0(1,23,0), /* move COP0 Debug to $1 */ MIPS32_LUI(2,0xFFFF), /* $2 = 0xfffffeff */ MIPS32_ORI(2,2,0xFEFF), @@ -235,7 +235,7 @@ int mips_ejtag_read_debug(mips_ejtag_t *ejtag_info, u32* debug_reg) MIPS32_SW(2,0,15), /* sw $2,($15) */ MIPS32_LUI(1,UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $1 = MIPS32_PRACC_PARAM_OUT */ MIPS32_ORI(1,1,LOWER16(MIPS32_PRACC_PARAM_OUT)), - MIPS32_MFC0(2,23,0), /* move COP0 Debug to $1 */ + MIPS32_MFC0(2,23,0), /* move COP0 Debug to $2 */ MIPS32_SW(2,0,1), MIPS32_LW(2,0,15), MIPS32_LW(1,0,15), |