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| author | Øyvind Harboe <oyvind.harboe@zylin.com> | 2010-08-08 19:21:04 +0200 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2010-08-09 09:14:01 +0200 |
| commit | 3e71449adec41bf2a9f498d027aae0ba6e83721f (patch) | |
| tree | 5c3f3392e32d25009c4a97846dc1f3a40cea36c4 /src/target/trace.c | |
| parent | 1399e5f753256e7b5523f1eb260cdd7e95e80dee (diff) | |
| download | openocd_libswd-3e71449adec41bf2a9f498d027aae0ba6e83721f.tar.gz openocd_libswd-3e71449adec41bf2a9f498d027aae0ba6e83721f.tar.bz2 openocd_libswd-3e71449adec41bf2a9f498d027aae0ba6e83721f.tar.xz openocd_libswd-3e71449adec41bf2a9f498d027aae0ba6e83721f.zip | |
arm7/9: fix "reset run + halt"
if polling is off, then "reset run + halt" would fail
since halt incorrectly assumed the target was in the
reset state as it is the internal poll implementation
that moves the sw tracking of the target state out
of the reset state.
To reproduce:
> reset run; halt
JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)
BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Diffstat (limited to 'src/target/trace.c')
0 files changed, 0 insertions, 0 deletions