diff options
| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-04 19:21:14 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-04 19:21:14 -0800 |
| commit | 0073e7a69e55eb435fc2e274ba245a27779963e4 (patch) | |
| tree | 137d7a8f1bbdd53cebebdae49e91627679d476c1 /src/target/xscale.c | |
| parent | 31e3ea7c19d39589ac9a8b2220331206b6d1e25c (diff) | |
| download | openocd_libswd-0073e7a69e55eb435fc2e274ba245a27779963e4.tar.gz openocd_libswd-0073e7a69e55eb435fc2e274ba245a27779963e4.tar.bz2 openocd_libswd-0073e7a69e55eb435fc2e274ba245a27779963e4.tar.xz openocd_libswd-0073e7a69e55eb435fc2e274ba245a27779963e4.zip | |
ARM: rename ARMV4_5_MODE_* as ARM_MODE_*
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/xscale.c')
| -rw-r--r-- | src/target/xscale.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/target/xscale.c b/src/target/xscale.c index f52965a3..57b1081f 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -1701,7 +1701,7 @@ static int xscale_full_context(struct target *target) bool valid = true; struct reg *r; - if (mode == ARMV4_5_MODE_USR) + if (mode == ARM_MODE_USR) continue; /* check if there are invalid registers in the current mode @@ -1724,7 +1724,7 @@ static int xscale_full_context(struct target *target) /* get banked registers: r8 to r14; and SPSR * except in USR/SYS mode */ - if (mode != ARMV4_5_MODE_SYS) { + if (mode != ARM_MODE_SYS) { /* SPSR */ r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, 16); @@ -1777,7 +1777,7 @@ static int xscale_restore_banked(struct target *target) enum armv4_5_mode mode = armv4_5_number_to_mode(i); struct reg *r; - if (mode == ARMV4_5_MODE_USR) + if (mode == ARM_MODE_USR) continue; /* check if there are dirty registers in this mode */ @@ -1789,7 +1789,7 @@ static int xscale_restore_banked(struct target *target) } /* if not USR/SYS, check if the SPSR needs to be written */ - if (mode != ARMV4_5_MODE_SYS) + if (mode != ARM_MODE_SYS) { if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, 16).dirty) @@ -1817,7 +1817,7 @@ dirty: } /* send spsr if not in USR/SYS mode */ - if (mode != ARMV4_5_MODE_SYS) { + if (mode != ARM_MODE_SYS) { r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, 16); xscale_send_u32(target, buf_get_u32(r->value, 0, 32)); |