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authoroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-09-11 08:03:46 +0000
committeroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-09-11 08:03:46 +0000
commit00e900f8a1dff8d0aeacc8cdded995e0abae37c5 (patch)
tree057473a02a66ee88ec7edac8ff986d4867d74ce0 /src/target
parentf89d1cbfd64aab73684201a50a156afde87405f2 (diff)
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Nicolas Pitre <nico@cam.org> Dragonite support
git-svn-id: svn://svn.berlios.de/openocd/trunk@2693 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target')
-rw-r--r--src/target/arm966e.c3
-rw-r--r--src/target/arm966e.h2
-rw-r--r--src/target/feroceon.c89
-rw-r--r--src/target/target.c2
4 files changed, 76 insertions, 20 deletions
diff --git a/src/target/arm966e.c b/src/target/arm966e.c
index d8e82819..badcd4f2 100644
--- a/src/target/arm966e.c
+++ b/src/target/arm966e.c
@@ -32,9 +32,6 @@
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
-/* cli handling */
-int arm966e_register_commands(struct command_context_s *cmd_ctx);
-
/* forward declarations */
int arm966e_target_create(struct target_s *target, Jim_Interp *interp);
int arm966e_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
diff --git a/src/target/arm966e.h b/src/target/arm966e.h
index 64641eae..c7a5b1bb 100644
--- a/src/target/arm966e.h
+++ b/src/target/arm966e.h
@@ -34,6 +34,8 @@ typedef struct arm966e_common_s
uint32_t cp15_control_reg;
} arm966e_common_t;
+extern int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, jtag_tap_t *tap);
+extern int arm966e_register_commands(struct command_context_s *cmd_ctx);
extern int arm966e_read_cp15(target_t *target, int reg_addr, uint32_t *value);
extern int arm966e_write_cp15(target_t *target, int reg_addr, uint32_t value);
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index ee96049d..6a673b71 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -1,5 +1,5 @@
/***************************************************************************
- * Copyright (C) 2008 by Marvell Semiconductors, Inc. *
+ * Copyright (C) 2008-2009 by Marvell Semiconductors, Inc. *
* Written by Nicolas Pitre <nico@marvell.com> *
* *
* Copyright (C) 2008 by Hongtao Zheng *
@@ -22,10 +22,10 @@
***************************************************************************/
/*
- * Marvell Feroceon support, including Orion and Kirkwood SOCs.
+ * Marvell Feroceon/Dragonite support.
*
- * The Feroceon core mimics the ARM926 ICE interface with the following
- * differences:
+ * The Feroceon core, as found in the Orion and Kirkwood SoCs amongst others,
+ * mimics the ARM926 ICE interface with the following differences:
*
* - the MOE (method of entry) reporting is not implemented
*
@@ -43,6 +43,9 @@
*
* - the DCC channel is half duplex (only one FIFO for both directions) with
* seemingly no proper flow control.
+ *
+ * The Dragonite core is the non-mmu version based on the ARM966 model, and
+ * it shares the above issues as well.
*/
#ifdef HAVE_CONFIG_H
@@ -50,11 +53,13 @@
#endif
#include "arm926ejs.h"
+#include "arm966e.h"
#include "target_type.h"
int feroceon_examine(struct target_s *target);
int feroceon_target_create(struct target_s *target, Jim_Interp *interp);
+int dragonite_target_create(struct target_s *target, Jim_Interp *interp);
int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer);
int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int feroceon_quit(void);
@@ -111,6 +116,44 @@ target_type_t feroceon_target =
.quit = feroceon_quit
};
+target_type_t dragonite_target =
+{
+ .name = "dragonite",
+
+ .poll = arm7_9_poll,
+ .arch_state = armv4_5_arch_state,
+
+ .target_request_data = arm7_9_target_request_data,
+
+ .halt = arm7_9_halt,
+ .resume = arm7_9_resume,
+ .step = arm7_9_step,
+
+ .assert_reset = feroceon_assert_reset,
+ .deassert_reset = arm7_9_deassert_reset,
+ .soft_reset_halt = arm7_9_soft_reset_halt,
+
+ .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+
+ .read_memory = arm7_9_read_memory,
+ .write_memory = arm7_9_write_memory,
+ .bulk_write_memory = feroceon_bulk_write_memory,
+ .checksum_memory = arm7_9_checksum_memory,
+ .blank_check_memory = arm7_9_blank_check_memory,
+
+ .run_algorithm = armv4_5_run_algorithm,
+
+ .add_breakpoint = arm7_9_add_breakpoint,
+ .remove_breakpoint = arm7_9_remove_breakpoint,
+ .add_watchpoint = arm7_9_add_watchpoint,
+ .remove_watchpoint = arm7_9_remove_watchpoint,
+
+ .register_commands = arm966e_register_commands,
+ .target_create = dragonite_target_create,
+ .init_target = feroceon_init_target,
+ .examine = feroceon_examine,
+ .quit = feroceon_quit
+};
int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, uint32_t instr)
{
@@ -632,16 +675,10 @@ int feroceon_quit(void)
return ERROR_OK;
}
-int feroceon_target_create(struct target_s *target, Jim_Interp *interp)
+void feroceon_common_setup(struct target_s *target)
{
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
- arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
-
- arm926ejs_init_arch_info(target, arm926ejs, target->tap);
-
- armv4_5 = target->arch_info;
- arm7_9 = armv4_5->arch_info;
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm7_9_common_t *arm7_9 = armv4_5->arch_info;
/* override some insn sequence functions */
arm7_9->change_to_arm = feroceon_change_to_arm;
@@ -661,10 +698,6 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp)
/* MOE is not implemented */
arm7_9->examine_debug_reason = feroceon_examine_debug_reason;
- /* the standard ARM926 methods don't always work (don't ask...) */
- arm926ejs->read_cp15 = feroceon_read_cp15;
- arm926ejs->write_cp15 = feroceon_write_cp15;
-
/* Note: asserting DBGRQ might not win over the undef exception.
If that happens then just use "arm7_9 dbgrq disable". */
arm7_9->use_dbgrq = 1;
@@ -673,6 +706,28 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp)
/* only one working comparator */
arm7_9->wp_available_max = 1;
arm7_9->wp1_used_default = -1;
+}
+
+int feroceon_target_create(struct target_s *target, Jim_Interp *interp)
+{
+ arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
+
+ arm926ejs_init_arch_info(target, arm926ejs, target->tap);
+ feroceon_common_setup(target);
+
+ /* the standard ARM926 methods don't always work (don't ask...) */
+ arm926ejs->read_cp15 = feroceon_read_cp15;
+ arm926ejs->write_cp15 = feroceon_write_cp15;
+
+ return ERROR_OK;
+}
+
+int dragonite_target_create(struct target_s *target, Jim_Interp *interp)
+{
+ arm966e_common_t *arm966e = calloc(1,sizeof(arm966e_common_t));
+
+ arm966e_init_arch_info(target, arm966e, target->tap);
+ feroceon_common_setup(target);
return ERROR_OK;
}
diff --git a/src/target/target.c b/src/target/target.c
index 7689c5e6..0bce8279 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -84,6 +84,7 @@ extern target_type_t arm966e_target;
extern target_type_t arm926ejs_target;
extern target_type_t fa526_target;
extern target_type_t feroceon_target;
+extern target_type_t dragonite_target;
extern target_type_t xscale_target;
extern target_type_t cortexm3_target;
extern target_type_t cortexa8_target;
@@ -101,6 +102,7 @@ target_type_t *target_types[] =
&arm926ejs_target,
&fa526_target,
&feroceon_target,
+ &dragonite_target,
&xscale_target,
&cortexm3_target,
&cortexa8_target,