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authormlu <mlu@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-09-14 22:41:47 +0000
committermlu <mlu@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-09-14 22:41:47 +0000
commit45674af63ad9ab9029abeff18237b9421dc0356a (patch)
tree02bfcb3db01e6b7ec3cf59b893d4714e0259694a /src/target
parentd4e4d65d284fa0347e601f30aebf4291074d9888 (diff)
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Check return values to avoid infinite wait in loop on error.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2709 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target')
-rw-r--r--src/target/cortex_a8.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index e73994e9..ae97f87e 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -153,7 +153,7 @@ mdw 0x54011080 4
int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
{
uint32_t dscr;
- int retvalue;
+ int retval;
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
armv7a_common_t *armv7a = armv4_5->arch_info;
@@ -162,8 +162,10 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
do
{
- retvalue = mem_ap_read_atomic_u32(swjdp,
+ retval = mem_ap_read_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+ if (retval != ERROR_OK)
+ return retval;
}
while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
@@ -171,12 +173,14 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
do
{
- retvalue = mem_ap_read_atomic_u32(swjdp,
+ retval = mem_ap_read_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+ if (retval != ERROR_OK)
+ return retval;
}
while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
- return retvalue;
+ return retval;
}
/**************************************************************************