a little bit more error handling in ARM11

git-svn-id: svn://svn.berlios.de/openocd/trunk@1542 b42882b7-edfa-0310-969c-e2dbd0fdcd60

3 files changed, 54 insertions, 21 deletions

diff --git a/src/target/arm11.c b/src/target/arm11.c
index d152880e..de9aecdd 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -48,7 +48,7 @@
 #define FNC_INFO_NOTIMPLEMENTED
 #endif
 
-static void arm11_on_enter_debug_state(arm11_common_t * arm11);
+static int arm11_on_enter_debug_state(arm11_common_t * arm11);
 
 bool	arm11_config_memwrite_burst				= true;
 bool	arm11_config_memwrite_error_fatal		= true;
@@ -313,16 +313,18 @@ reg_t arm11_gdb_dummy_fps_reg =
  *					available a pointer to a word holding the
  *					DSCR can be passed. Otherwise use NULL.
  */
-void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
+int arm11_check_init(arm11_common_t * arm11, u32 * dscr)
 {
 	FNC_INFO;
+	int retval;
 
 	u32			dscr_local_tmp_copy;
 
 	if (!dscr)
 	{
 		dscr = &dscr_local_tmp_copy;
-		*dscr = arm11_read_DSCR(arm11);
+		if ((retval=arm11_read_DSCR(arm11, dscr))!=ERROR_OK)
+			return retval;
 	}
 
 	if (!(*dscr & ARM11_DSCR_MODE_SELECT))
@@ -353,6 +355,8 @@ void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
 
 		arm11_sc7_clear_vbw(arm11);
 	}
+
+	return ERROR_OK;
 }
 
 
@@ -366,7 +370,7 @@ void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
   * or on other occasions that stop the processor.
   *
   */
-static void arm11_on_enter_debug_state(arm11_common_t * arm11)
+static int arm11_on_enter_debug_state(arm11_common_t * arm11)
 {
 	FNC_INFO;
 
@@ -378,8 +382,9 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
 	}}
 
 	/* Save DSCR */
-
-	R(DSCR) = arm11_read_DSCR(arm11);
+	int retval;
+	if ((retval=arm11_read_DSCR(arm11, &R(DSCR)))!=ERROR_OK)
+		return retval;
 
 	/* Save wDTR */
 
@@ -514,6 +519,8 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
 	arm11_run_instr_data_finish(arm11);
 
 	arm11_dump_reg_changes(arm11);
+
+	return ERROR_OK;
 }
 
 void arm11_dump_reg_changes(arm11_common_t * arm11)
@@ -546,7 +553,7 @@ void arm11_dump_reg_changes(arm11_common_t * arm11)
   * This is called in preparation for the RESTART function.
   *
   */
-void arm11_leave_debug_state(arm11_common_t * arm11)
+int arm11_leave_debug_state(arm11_common_t * arm11)
 {
 	FNC_INFO;
 
@@ -572,7 +579,12 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
 	/* spec says clear wDTR and rDTR; we assume they are clear as
 	   otherwise our programming would be sloppy */
 	{
-		u32 DSCR = arm11_read_DSCR(arm11);
+		u32 DSCR;
+		int retval;
+		if ((retval=arm11_read_DSCR(arm11, &DSCR))!=ERROR_OK)
+		{
+			return retval;
+		}
 
 		if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
 		{
@@ -632,6 +644,8 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
 	}
 
 	arm11_record_register_history(arm11);
+
+	return ERROR_OK;
 }
 
 void arm11_record_register_history(arm11_common_t * arm11)
@@ -658,11 +672,15 @@ int arm11_poll(struct target_s *target)
 	if (arm11->trst_active)
 		return ERROR_OK;
 
-	u32	dscr = arm11_read_DSCR(arm11);
+	u32	dscr;
+	int retval;
+	if ((retval=arm11_read_DSCR(arm11, &dscr))!=ERROR_OK)
+		return retval;
 
 	LOG_DEBUG("DSCR %08x", dscr);
 
-	arm11_check_init(arm11, &dscr);
+	if ((retval=arm11_check_init(arm11, &dscr))!=ERROR_OK)
+		return retval;
 
 	if (dscr & ARM11_DSCR_CORE_HALTED)
 	{
@@ -747,7 +765,10 @@ int arm11_halt(struct target_s *target)
 
 	while (1)
 	{
-		dscr = arm11_read_DSCR(arm11);
+		int retval;
+		retval = arm11_read_DSCR(arm11, &dscr);
+		if (retval!=ERROR_OK)
+			return retval;
 
 		if (dscr & ARM11_DSCR_CORE_HALTED)
 			break;
@@ -774,7 +795,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
 	int retval = ERROR_OK;
 
 	FNC_INFO;
-	
+
 	//	  LOG_DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d",
 	//	current, address, handle_breakpoints, debug_execution);
 
@@ -851,7 +872,10 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
 
 	while (1)
 	{
-		u32 dscr = arm11_read_DSCR(arm11);
+		u32 dscr;
+		retval = arm11_read_DSCR(arm11, &dscr);
+		if (retval!=ERROR_OK)
+			return retval;
 
 		LOG_DEBUG("DSCR %08x", dscr);
 
@@ -961,7 +985,7 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
 			R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;		/* should be redundant */
 		else
 			R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
-			
+
 
 		arm11_leave_debug_state(arm11);
 
@@ -978,7 +1002,10 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
 
 		while (1)
 		{
-			u32 dscr = arm11_read_DSCR(arm11);
+			u32 dscr;
+			retval = arm11_read_DSCR(arm11, &dscr);
+			if (retval!=ERROR_OK)
+				return retval;
 
 			LOG_DEBUG("DSCR %08x", dscr);
 
@@ -1987,7 +2014,7 @@ int arm11_register_commands(struct command_context_s *cmd_ctx)
 
 	RC_FINAL_BOOL(		"no_increment",			"Don't increment address on multi-read/-write (default: disabled)",
 						memrw_no_increment)
-						
+
 	RC_FINAL_BOOL(		"step_irq_enable",		"Enable interrupts while stepping (default: disabled)",
 						step_irq_enable)
 
diff --git a/src/target/arm11.h b/src/target/arm11.h
index b22baabc..1535849f 100644
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -91,7 +91,7 @@ typedef struct arm11_common_s
 	bool	trst_active;
 	bool	halt_requested;					/**< Keep track if arm11_halt() calls occured
 												 during reset. Otherwise do it ASAP. */
-												 
+
 	bool	simulate_reset_on_next_halt;	/**< Perform cleanups of the ARM state on next halt */
 
 	/** \name Shadow registers to save processor state */
@@ -239,7 +239,7 @@ void arm11_setup_field			(arm11_common_t * arm11, int num_bits, void * in_data,
 void arm11_add_IR				(arm11_common_t * arm11, u8 instr, tap_state_t state);
 void arm11_add_debug_SCAN_N		(arm11_common_t * arm11, u8 chain, tap_state_t state);
 void arm11_add_debug_INST		(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state);
-u32  arm11_read_DSCR			(arm11_common_t * arm11);
+int arm11_read_DSCR			(arm11_common_t * arm11, u32 *dscr);
 void arm11_write_DSCR			(arm11_common_t * arm11, u32 dscr);
 
 enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);
diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c
index 9cc8ad03..73607176 100644
--- a/src/target/arm11_dbgtap.c
+++ b/src/target/arm11_dbgtap.c
@@ -216,7 +216,7 @@ void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state
  *
  * \remarks			This is a stand-alone function that executes the JTAG command queue.
  */
-u32 arm11_read_DSCR(arm11_common_t * arm11)
+int arm11_read_DSCR(arm11_common_t * arm11, u32 *value)
 {
 	arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
 
@@ -229,14 +229,20 @@ u32 arm11_read_DSCR(arm11_common_t * arm11)
 
 	arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
 
-	jtag_execute_queue();
+	int retval;
+	if ((retval=jtag_execute_queue())!=ERROR_OK)
+	{
+		return retval;
+	}
 
 	if (arm11->last_dscr != dscr)
 		JTAG_DEBUG("DSCR  = %08x (OLD %08x)", dscr, arm11->last_dscr);
 
 	arm11->last_dscr = dscr;
 
-	return dscr;
+	*value=dscr;
+
+	return retval;
 }
 
 /** Write the Debug Status and Control Register (DSCR)