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authorDavid Brownell <dbrownell@users.sourceforge.net>2010-01-07 16:39:32 -0800
committerDavid Brownell <dbrownell@users.sourceforge.net>2010-01-07 16:39:32 -0800
commit82c0fb527783a56f7cf82e21b85546b425378b00 (patch)
treec756b4994fe3a28c2e2f9d5b5058a5dd293622f8 /src/target
parente7965cd3eb6204e618f9555331b7172e3dba7df8 (diff)
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ARM966: help/usage updates
Usage syntax messages have the same EBNF as the User's Guide; there should be no angle brackets in either place. Fix the User's Guide to say where the magic CP15 bits are defined; and add comments in case someone provides mcr/mrc methods. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target')
-rw-r--r--src/target/arm966e.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/src/target/arm966e.c b/src/target/arm966e.c
index 82be7380..86af0f60 100644
--- a/src/target/arm966e.c
+++ b/src/target/arm966e.c
@@ -68,6 +68,13 @@ static int arm966e_verify_pointer(struct command_context *cmd_ctx,
return ERROR_OK;
}
+/*
+ * REVISIT: The "read_cp15" and "write_cp15" commands could hook up
+ * to eventual mrc() and mcr() routines ... the reg_addr values being
+ * constructed (for CP15 only) from Opcode_1, Opcode_2, and CRn values.
+ * See section 7.3 of the ARM966E-S TRM.
+ */
+
static int arm966e_read_cp15(struct target *target, int reg_addr, uint32_t *value)
{
int retval = ERROR_OK;
@@ -86,6 +93,9 @@ static int arm966e_read_cp15(struct target *target, int reg_addr, uint32_t *valu
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
+ /* REVISIT: table 7-2 shows that bits 31-31 need to be
+ * specified for accessing BIST registers ...
+ */
fields[0].out_value = NULL;
fields[0].in_value = NULL;
@@ -227,7 +237,7 @@ static const struct command_registration arm966e_exec_command_handlers[] = {
.name = "cp15",
.handler = arm966e_handle_cp15_command,
.mode = COMMAND_EXEC,
- .usage = "<opcode> [value]",
+ .usage = "regnum [value]",
.help = "display/modify cp15 register",
},
COMMAND_REGISTRATION_DONE