David Brownell <david-b@pacbell.net> whitespace fixes.

git-svn-id: svn://svn.berlios.de/openocd/trunk@1690 b42882b7-edfa-0310-969c-e2dbd0fdcd60

11 files changed, 95 insertions, 196 deletions

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 5c4ba16a..b04a17f7 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -113,13 +113,12 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
 	fields[0].num_bits = 1;
 	fields[0].out_value = &instruction_buf;
 	fields[0].in_value = NULL;
-	
 
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 32;
 	fields[1].out_value = out_buf;
 	fields[1].in_value = NULL;
-	
+
 	if (in)
 	{
 		u8 tmp[4];
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 3fe8efa9..b7f4a4df 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1287,7 +1287,7 @@ int arm7_9_full_context(target_t *target)
 	/* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
 	 * SYS shares registers with User, so we don't touch SYS
 	 */
-	for(i = 0; i < 6; i++)
+	for (i = 0; i < 6; i++)
 	{
 		u32 mask = 0;
 		u32* reg_p[16];
diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h
index 9b497edc..d5b0487f 100644
--- a/src/target/arm7_9_common.h
+++ b/src/target/arm7_9_common.h
@@ -41,10 +41,10 @@
 typedef struct arm7_9_common_s
 {
 	u32 common_magic;
-	
+
 	arm_jtag_t jtag_info;
 	reg_cache_t *eice_cache;
-	
+
 	u32 arm_bkpt;
 	u16 thumb_bkpt;
 	int sw_breakpoints_added;
@@ -58,32 +58,32 @@ typedef struct arm7_9_common_s
 	int dbgreq_adjust_pc;
 	int use_dbgrq;
 	int need_bypass_before_restart;
-	
+
 	etm_context_t *etm_ctx;
-	
+
 	int has_single_step;
 	int has_monitor_mode;
 	int has_vector_catch;
-	
+
 	int debug_entry_from_reset;
-	
+
 	struct working_area_s *dcc_working_area;
-	
+
 	int fast_memory_access;
 	int dcc_downloads;
 
 	int (*examine_debug_reason)(target_t *target);
-	
+
 	void (*change_to_arm)(target_t *target, u32 *r0, u32 *pc);
-	
+
 	void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]);
 	void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void *buffer, int size);
 	void (*read_xpsr)(target_t *target, u32 *xpsr, int spsr);
-	
+
 	void (*write_xpsr)(target_t *target, u32 xpsr, int spsr);
 	void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int spsr);
 	void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
-	
+
 	void (*load_word_regs)(target_t *target, u32 mask);
 	void (*load_hword_reg)(target_t *target, int num);
 	void (*load_byte_reg)(target_t *target, int num);
@@ -91,22 +91,22 @@ typedef struct arm7_9_common_s
 	void (*store_word_regs)(target_t *target, u32 mask);
 	void (*store_hword_reg)(target_t *target, int num);
 	void (*store_byte_reg)(target_t *target, int num);
-	
+
 	void (*write_pc)(target_t *target, u32 pc);
 	void (*branch_resume)(target_t *target);
 	void (*branch_resume_thumb)(target_t *target);
-	
+
 	void (*enable_single_step)(target_t *target, u32 next_pc);
 	void (*disable_single_step)(target_t *target);
-	
+
 	void (*set_special_dbgrq)(target_t *target);
 
 	void (*pre_debug_entry)(target_t *target);
 	void (*post_debug_entry)(target_t *target);
-	
+
 	void (*pre_restore_context)(target_t *target);
 	void (*post_restore_context)(target_t *target);
-	
+
 	armv4_5_common_t armv4_5_common;
 	void *arch_info;
 
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index 268d09e5..098b3732 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -115,13 +115,11 @@ int arm7tdmi_examine_debug_reason(target_t *target)
 		fields[0].num_bits = 1;
 		fields[0].out_value = NULL;
 		fields[0].in_value = &breakpoint;
-		
 
 		fields[1].tap = arm7_9->jtag_info.tap;
 		fields[1].num_bits = 32;
 		fields[1].out_value = NULL;
 		fields[1].in_value = databus;
-		
 
 		if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
 		{
@@ -194,15 +192,12 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 	fields[0].num_bits = 1;
 	fields[0].out_value = NULL;
 	fields[0].in_value = NULL;
-	
-
 
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 32;
 	fields[1].out_value = NULL;
 	u8 tmp[4];
 	fields[1].in_value = tmp;
-	
 
 	jtag_add_dr_scan_now(2, fields, TAP_INVALID);
 
@@ -286,14 +281,12 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
 	fields[0].num_bits = 1;
 	fields[0].out_value = NULL;
 	fields[0].in_value = NULL;
-	
 
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 32;
 	fields[1].out_value = NULL;
 	u8 tmp[4];
 	fields[1].in_value = tmp;
-	
 
 	jtag_add_dr_scan_now(2, fields, TAP_INVALID);
 
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index d83f54ba..af26a2fc 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -114,25 +114,21 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
 	fields[0].num_bits = 1;
 	fields[0].out_value = &access_type_buf;
 	fields[0].in_value = NULL;
-	
 
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 32;
 	fields[1].out_value = NULL;
 	fields[1].in_value = NULL;
-	
 
 	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 6;
 	fields[2].out_value = &reg_addr_buf;
 	fields[2].in_value = NULL;
-	
 
 	fields[3].tap = jtag_info->tap;
 	fields[3].num_bits = 1;
 	fields[3].out_value = &nr_w_buf;
 	fields[3].in_value = NULL;
-	
 
 	jtag_add_dr_scan(4, fields, TAP_INVALID);
 
@@ -171,43 +167,23 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
 	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 1;
 	fields[0].out_value = &access_type_buf;
-
 	fields[0].in_value = NULL;
 
-
-	
-
-
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 32;
 	fields[1].out_value = value_buf;
-
 	fields[1].in_value = NULL;
 
-
-	
-
-
 	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 6;
 	fields[2].out_value = &reg_addr_buf;
-
 	fields[2].in_value = NULL;
 
-
-	
-
-
 	fields[3].tap = jtag_info->tap;
 	fields[3].num_bits = 1;
 	fields[3].out_value = &nr_w_buf;
-
 	fields[3].in_value = NULL;
 
-
-	
-
-
 	jtag_add_dr_scan(4, fields, TAP_INVALID);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
@@ -238,43 +214,23 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
 	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 1;
 	fields[0].out_value = &access_type_buf;
-
 	fields[0].in_value = NULL;
 
-
-	
-
-
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 32;
 	fields[1].out_value = cp15_opcode_buf;
-
 	fields[1].in_value = NULL;
 
-
-	
-
-
 	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 6;
 	fields[2].out_value = &reg_addr_buf;
-
 	fields[2].in_value = NULL;
 
-
-	
-
-
 	fields[3].tap = jtag_info->tap;
 	fields[3].num_bits = 1;
 	fields[3].out_value = &nr_w_buf;
-
 	fields[3].in_value = NULL;
 
-
-	
-
-
 	jtag_add_dr_scan(4, fields, TAP_INVALID);
 
 	arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
@@ -621,7 +577,7 @@ int arm920t_soft_reset_halt(struct target_s *target)
 	arm920t_common_t *arm920t = arm9tdmi->arch_info;
 	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
-	if((retval = target_halt(target)) != ERROR_OK)
+	if ((retval = target_halt(target)) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -633,7 +589,7 @@ int arm920t_soft_reset_halt(struct target_s *target)
 		if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 		{
 			embeddedice_read_reg(dbg_stat);
-			if((retval = jtag_execute_queue()) != ERROR_OK)
+			if ((retval = jtag_execute_queue()) != ERROR_OK)
 			{
 				return retval;
 			}
@@ -676,7 +632,7 @@ int arm920t_soft_reset_halt(struct target_s *target)
 	arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 	arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
-	if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
+	if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -814,7 +770,7 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
 
 	/* disable MMU and Caches */
 	arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
-	if((retval = jtag_execute_queue()) != ERROR_OK)
+	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -877,7 +833,7 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
 
 			/* read D RAM and CAM content */
 			arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
-			if((retval = jtag_execute_queue()) != ERROR_OK)
+			if ((retval = jtag_execute_queue()) != ERROR_OK)
 			{
 				return retval;
 			}
@@ -963,7 +919,7 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
 
 			/* read I RAM and CAM content */
 			arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
-			if((retval = jtag_execute_queue()) != ERROR_OK)
+			if ((retval = jtag_execute_queue()) != ERROR_OK)
 			{
 				return retval;
 			}
@@ -1066,7 +1022,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 
 	/* disable MMU and Caches */
 	arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
-	if((retval = jtag_execute_queue()) != ERROR_OK)
+	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -1076,7 +1032,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 
 	/* read CP15 test state register */
 	arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
-	if((retval = jtag_execute_queue()) != ERROR_OK)
+	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -1097,7 +1053,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 
 	/* read D TLB lockdown stored to r1 */
 	arm9tdmi_read_core_regs(target, 0x2, regs_p);
-	if((retval = jtag_execute_queue()) != ERROR_OK)
+	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -1126,7 +1082,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 
 		/* read D TLB CAM content stored to r2-r9 */
 		arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
-		if((retval = jtag_execute_queue()) != ERROR_OK)
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -1161,7 +1117,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 
 		/* read D TLB RAM content stored to r2 and r3 */
 		arm9tdmi_read_core_regs(target, 0xc, regs_p);
-		if((retval = jtag_execute_queue()) != ERROR_OK)
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -1193,7 +1149,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 
 	/* read I TLB lockdown stored to r1 */
 	arm9tdmi_read_core_regs(target, 0x2, regs_p);
-	if((retval = jtag_execute_queue()) != ERROR_OK)
+	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -1222,7 +1178,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 
 		/* read I TLB CAM content stored to r2-r9 */
 		arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
-		if((retval = jtag_execute_queue()) != ERROR_OK)
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -1257,7 +1213,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 
 		/* read I TLB RAM content stored to r2 and r3 */
 		arm9tdmi_read_core_regs(target, 0xc, regs_p);
-		if((retval = jtag_execute_queue()) != ERROR_OK)
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -1347,7 +1303,7 @@ int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
 				command_print(cmd_ctx, "couldn't access reg %i", address);
 				return ERROR_OK;
 			}
-			if((retval = jtag_execute_queue()) != ERROR_OK)
+			if ((retval = jtag_execute_queue()) != ERROR_OK)
 			{
 				return retval;
 			}
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index f05087e4..c943f2fc 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -133,7 +133,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
 	buf_set_u32(address_buf, 0, 14, address);
 
 	jtag_add_end_state(TAP_IDLE);
-	if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+	if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -151,20 +151,16 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
 	fields[1].out_value = &access;
 	fields[1].in_value = &access;
 
-
 	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 14;
 	fields[2].out_value = address_buf;
 	fields[2].in_value = NULL;
 
-
-
 	fields[3].tap = jtag_info->tap;
 	fields[3].num_bits = 1;
 	fields[3].out_value = &nr_w_buf;
 	fields[3].in_value = NULL;
 
-
 	jtag_add_dr_scan(4, fields, TAP_INVALID);
 
 	/*TODO: add timeout*/
@@ -177,7 +173,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
 
 		*value=le_to_h_u32(tmp);
 
-		if((retval = jtag_execute_queue()) != ERROR_OK)
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -209,7 +205,7 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
 	buf_set_u32(value_buf, 0, 32, value);
 
 	jtag_add_end_state(TAP_IDLE);
-	if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+	if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -218,43 +214,23 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
 	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = value_buf;
-
 	fields[0].in_value = NULL;
 
-
-
-
-
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 1;
 	fields[1].out_value = &access;
-
 	fields[1].in_value = &access;
 
-
-
-
-
 	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 14;
 	fields[2].out_value = address_buf;
-
 	fields[2].in_value = NULL;
 
-
-
-
-
 	fields[3].tap = jtag_info->tap;
 	fields[3].num_bits = 1;
 	fields[3].out_value = &nr_w_buf;
-
 	fields[3].in_value = NULL;
 
-
-
-
-
 	jtag_add_dr_scan(4, fields, TAP_INVALID);
 	/*TODO: add timeout*/
 	do
@@ -263,7 +239,7 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
 		access = 0;
 		nr_w_buf = 0;
 		jtag_add_dr_scan(4, fields, TAP_INVALID);
-		if((retval = jtag_execute_queue()) != ERROR_OK)
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -595,7 +571,7 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
 	arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
-	if((retval = target_halt(target)) != ERROR_OK)
+	if ((retval = target_halt(target)) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -607,7 +583,7 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
 		if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 		{
 			embeddedice_read_reg(dbg_stat);
-			if((retval = jtag_execute_queue()) != ERROR_OK)
+			if ((retval = jtag_execute_queue()) != ERROR_OK)
 			{
 				return retval;
 			}
@@ -812,7 +788,7 @@ int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd,
 			command_print(cmd_ctx, "couldn't access register");
 			return ERROR_OK;
 		}
-		if((retval = jtag_execute_queue()) != ERROR_OK)
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
 		}
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 5098b3e2..e0a31139 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -128,41 +128,26 @@ int arm9tdmi_examine_debug_reason(target_t *target)
 		fields[0].tap = arm7_9->jtag_info.tap;
 		fields[0].num_bits = 32;
 		fields[0].out_value = NULL;
-
 		fields[0].in_value = databus;
 
-
-		
-
-
 		fields[1].tap = arm7_9->jtag_info.tap;
 		fields[1].num_bits = 3;
 		fields[1].out_value = NULL;
-
 		fields[1].in_value = &debug_reason;
 
-
-		
-
-
 		fields[2].tap = arm7_9->jtag_info.tap;
 		fields[2].num_bits = 32;
 		fields[2].out_value = NULL;
-
 		fields[2].in_value = instructionbus;
 
-
-		
-
-
-		if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
+		if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
 		{
 			return retval;
 		}
 		arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
 
 		jtag_add_dr_scan(3, fields, TAP_DRPAUSE);
-		if((retval = jtag_execute_queue()) != ERROR_OK)
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -206,7 +191,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
 		buf_set_u32(&sysspeed_buf, 2, 1, 1);
 
 	jtag_add_end_state(TAP_DRPAUSE);
-	if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+	if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -217,20 +202,16 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
 	fields[0].num_bits = 32;
 	fields[0].out_value = out_buf;
 	fields[0].in_value = NULL;
-	
 
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 3;
 	fields[1].out_value = &sysspeed_buf;
 	fields[1].in_value = NULL;
-	
-
 
 	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 32;
 	fields[2].out_value = instr_buf;
 	fields[2].in_value = NULL;
-	
 
 	if (in)
 	{
@@ -249,7 +230,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 	{
-		if((retval = jtag_execute_queue()) != ERROR_OK)
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -273,7 +254,7 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 	scan_field_t fields[3];
 
 	jtag_add_end_state(TAP_DRPAUSE);
-	if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+	if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -285,19 +266,16 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 	fields[0].out_value = NULL;
 	u8 tmp[4];
 	fields[0].in_value = tmp;
-	
 
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 3;
 	fields[1].out_value = NULL;
 	fields[1].in_value = NULL;
-	
 
 	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 32;
 	fields[2].out_value = NULL;
 	fields[2].in_value = NULL;
-	
 
 	jtag_add_dr_scan_now(3, fields, TAP_INVALID);
 
@@ -307,7 +285,7 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 	{
-		if((retval = jtag_execute_queue()) != ERROR_OK)
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -338,7 +316,7 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
 	scan_field_t fields[3];
 
 	jtag_add_end_state(TAP_DRPAUSE);
-	if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+	if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -350,19 +328,16 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
 	fields[0].out_value = NULL;
 	u8 tmp[4];
 	fields[0].in_value = tmp;
-	
 
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 3;
 	fields[1].out_value = NULL;
 	fields[1].in_value = NULL;
-	
 
 	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 32;
 	fields[2].out_value = NULL;
 	fields[2].in_value = NULL;
-	
 
 	jtag_add_dr_scan_now(3, fields, TAP_INVALID);
 
@@ -373,7 +348,7 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 	{
-		if((retval = jtag_execute_queue()) != ERROR_OK)
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -435,7 +410,7 @@ void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
 	/* NOP fetched, BX in Execute (1) */
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 
-	if((retval = jtag_execute_queue()) != ERROR_OK)
+	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		return;
 	}
@@ -1047,7 +1022,7 @@ int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, cha
 			for (i = 0; i < argc; i++)
 			{
 				/* go through list of vectors */
-				for(j = 0; arm9tdmi_vectors[j].name; j++)
+				for (j = 0; arm9tdmi_vectors[j].name; j++)
 				{
 					if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0)
 					{
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 4a7fd7a4..1144c7f1 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -428,23 +428,23 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *
 
 	for (i = 0; i < count; i++)
 	{
-		if(thumb)
+		if (thumb)
 		{
-			if((retval = target_read_u16(target, address, &thumb_opcode)) != ERROR_OK)
+			if ((retval = target_read_u16(target, address, &thumb_opcode)) != ERROR_OK)
 			{
 				return retval;
 			}
-			if((retval = thumb_evaluate_opcode(thumb_opcode, address, &cur_instruction)) != ERROR_OK)
+			if ((retval = thumb_evaluate_opcode(thumb_opcode, address, &cur_instruction)) != ERROR_OK)
 			{
 				return retval;
 			}
 		}
 		else {
-			if((retval = target_read_u32(target, address, &opcode)) != ERROR_OK)
+			if ((retval = target_read_u32(target, address, &opcode)) != ERROR_OK)
 			{
 				return retval;
 			}
-			if((retval = arm_evaluate_opcode(opcode, address, &cur_instruction)) != ERROR_OK)
+			if ((retval = arm_evaluate_opcode(opcode, address, &cur_instruction)) != ERROR_OK)
 			{
 				return retval;
 			}
@@ -502,7 +502,7 @@ static int armv4_5_run_algorithm_completion(struct target_s *target, u32 exit_po
 	int retval;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 
-	if((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
+	if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -564,7 +564,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
 
 	for (i = 0; i < num_mem_params; i++)
 	{
-		if((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
+		if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -585,7 +585,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
 			exit(-1);
 		}
 
-		if((retval = armv4_5_set_core_reg(reg, reg_params[i].value)) != ERROR_OK)
+		if ((retval = armv4_5_set_core_reg(reg, reg_params[i].value)) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -616,7 +616,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
 		return ERROR_TARGET_FAILURE;
 	}
 
-	if((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
+	if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -631,7 +631,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
 	for (i = 0; i < num_mem_params; i++)
 	{
 		if (mem_params[i].direction != PARAM_OUT)
-			if((retvaltemp = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
+			if ((retvaltemp = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
 			{
 					retval = retvaltemp;
 			}
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 59f4af99..128242ea 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -29,10 +29,10 @@
 
 typedef enum armv4_5_mode
 {
-	ARMV4_5_MODE_USR = 16, 
-	ARMV4_5_MODE_FIQ = 17, 
-	ARMV4_5_MODE_IRQ = 18, 
-	ARMV4_5_MODE_SVC = 19, 
+	ARMV4_5_MODE_USR = 16,
+	ARMV4_5_MODE_FIQ = 17,
+	ARMV4_5_MODE_IRQ = 18,
+	ARMV4_5_MODE_SVC = 19,
 	ARMV4_5_MODE_ABT = 23,
 	ARMV4_5_MODE_UND = 27,
 	ARMV4_5_MODE_SYS = 31,
@@ -58,7 +58,7 @@ extern int armv4_5_core_reg_map[7][17];
 		cache->reg_list[armv4_5_core_reg_map[mode][num]]
 
 /* offsets into armv4_5 core register cache */
-enum 
+enum
 {
 	ARMV4_5_CPSR = 31,
 	ARMV4_5_SPSR_FIQ = 32,
@@ -85,7 +85,7 @@ typedef struct armv4_5_common_s
 typedef struct armv4_5_algorithm_s
 {
 	int common_magic;
-		
+
 	enum armv4_5_mode core_mode;
 	enum armv4_5_state core_state;
 } armv4_5_algorithm_t;
@@ -113,7 +113,7 @@ static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
 		case ARMV4_5_MODE_UND: return 5; break;
 		case ARMV4_5_MODE_SYS: return 6; break;
 		case ARMV4_5_MODE_ANY: return 0; break;	/* map MODE_ANY to user mode */
-		default: 
+		default:
 			LOG_ERROR("invalid mode value encountered");
 			return -1;
 	}
@@ -122,7 +122,7 @@ static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
 /* map linear number to mode bits */
 static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
 {
-	switch(number)
+	switch (number)
 	{
 		case 0: return ARMV4_5_MODE_USR; break;
 		case 1: return ARMV4_5_MODE_FIQ; break;
@@ -131,7 +131,7 @@ static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
 		case 4: return ARMV4_5_MODE_ABT; break;
 		case 5: return ARMV4_5_MODE_UND; break;
 		case 6: return ARMV4_5_MODE_SYS; break;
-		default: 
+		default:
 			LOG_ERROR("mode index out of bounds");
 			return ARMV4_5_MODE_ANY;
 	}
@@ -149,7 +149,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
 
 /* ARM mode instructions
  */
- 
+
 /* Store multiple increment after
  * Rn: base register
  * List: for each bit in list: store register
@@ -239,7 +239,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  * CRm: second coprocessor operand
  * op2: Second coprocessor opcode
  */
-#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) 
+#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 
 /* Move to coprocessor from ARM register
  * CP: Coprocessor number
@@ -249,7 +249,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  * CRm: second coprocessor operand
  * op2: Second coprocessor opcode
  */
-#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) 
+#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 
 /* Breakpoint instruction (ARMv5)
  * Im: 16-bit immediate
@@ -259,7 +259,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
 
 /* Thumb mode instructions
  */
- 
+
 /* Store register (Thumb mode)
  * Rd: source register
  * Rn: base register
@@ -277,12 +277,12 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  * List: for each bit in list: store register
  */
 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
- 
+
 /* Load register with PC relative addressing
  * Rd: register to load
  */
-#define ARMV4_5_T_LDR_PCREL(Rd)	((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16)) 
- 
+#define ARMV4_5_T_LDR_PCREL(Rd)	((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
+
 /* Move hi register (Thumb mode)
  * Rd: destination register
  * Rm: source register
diff --git a/src/target/armv4_5_cache.c b/src/target/armv4_5_cache.c
index 30a41d61..127420dc 100644
--- a/src/target/armv4_5_cache.c
+++ b/src/target/armv4_5_cache.c
@@ -63,7 +63,7 @@ int armv4_5_identify_cache(u32 cache_type_reg, armv4_5_cache_common_t *cache)
 		M = (cache_type_reg & 0x4) >> 2;
 		len = (cache_type_reg & 0x3);
 		multiplier = 2 + M;
-		
+
 		if ((assoc != 0) || (M != 1)) /* assoc 0 and M 1 means cache absent */
 		{
 			/* cache is present */
@@ -85,7 +85,7 @@ int armv4_5_identify_cache(u32 cache_type_reg, armv4_5_cache_common_t *cache)
 	{
 		cache->i_size = cache->d_u_size;
 	}
-	
+
 	return ERROR_OK;
 }
 
@@ -96,21 +96,21 @@ int armv4_5_handle_cache_info_command(struct command_context_s *cmd_ctx, armv4_5
 		command_print(cmd_ctx, "cache not yet identified");
 		return ERROR_OK;
 	}
-		
-	command_print(cmd_ctx, "cache type: 0x%1.1x, %s", armv4_5_cache->ctype, 
+
+	command_print(cmd_ctx, "cache type: 0x%1.1x, %s", armv4_5_cache->ctype,
 		(armv4_5_cache->separate) ? "separate caches" : "unified cache");
 
-	command_print(cmd_ctx, "D-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x", 
+	command_print(cmd_ctx, "D-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x",
 		armv4_5_cache->d_u_size.linelen,
 		armv4_5_cache->d_u_size.associativity,
 		armv4_5_cache->d_u_size.nsets,
 		armv4_5_cache->d_u_size.cachesize);
 
-	command_print(cmd_ctx, "I-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x", 
+	command_print(cmd_ctx, "I-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x",
 		armv4_5_cache->i_size.linelen,
 		armv4_5_cache->i_size.associativity,
 		armv4_5_cache->i_size.nsets,
 		armv4_5_cache->i_size.cachesize);
-	
+
 	return ERROR_OK;
 }
diff --git a/src/target/armv4_5_mmu.c b/src/target/armv4_5_mmu.c
index 869aabef..b108196e 100644
--- a/src/target/armv4_5_mmu.c
+++ b/src/target/armv4_5_mmu.c
@@ -89,9 +89,9 @@ u32 armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu
 			(first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
 			4, 1, (u8*)&second_lvl_descriptor);
 	}
-	
+
 	second_lvl_descriptor = target_buffer_get_u32(target, (u8*)&second_lvl_descriptor);
-	
+
 	LOG_DEBUG("2nd lvl desc: %8.8x", second_lvl_descriptor);
 
 	if ((second_lvl_descriptor & 0x3) == 0)
@@ -163,14 +163,14 @@ int armv4_5_mmu_write_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_m
 
 	/* disable MMU and data (or unified) cache */
 	armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
-	
+
 	retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
 
 	/* reenable MMU / cache */
 	armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
 		armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
 		armv4_5_mmu->armv4_5_cache.i_cache_enabled);
-	
+
 	return retval;
 }
 
@@ -182,7 +182,7 @@ int armv4_5_mmu_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd,
 	u32 cb;
 	int domain;
 	u32 ap;
-	
+
 	if (target->state != TARGET_HALTED)
 	{
 		command_print(cmd_ctx, "target must be stopped for \"virt2phys\" command");
@@ -211,11 +211,11 @@ int armv4_5_mmu_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd,
 			}
 			return ERROR_OK;
 		}
-	
+
 		command_print(cmd_ctx, "0x%8.8x -> 0x%8.8x, type: %s, cb: %i, domain: %i, ap: %2.2x",
 			va, pa, armv4_5_mmu_page_type_names[type], cb, domain, ap);
-	}			
-	
+	}
+
 	return ERROR_OK;
 }
 
@@ -272,7 +272,7 @@ int armv4_5_mmu_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, ch
 				break;
 			case ERROR_TARGET_NOT_HALTED:
 				command_print(cmd_ctx, "error: target must be halted for memory accesses");
-				break;			
+				break;
 			case ERROR_TARGET_DATA_ABORT:
 				command_print(cmd_ctx, "error: access caused data abort, system possibly corrupted");
 				break;
@@ -287,7 +287,7 @@ int armv4_5_mmu_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, ch
 	{
 		if (i%8 == 0)
 			output_len += snprintf(output + output_len, 128 - output_len, "0x%8.8x: ", address + (i*size));
-		
+
 		switch (size)
 		{
 			case 4:
@@ -309,7 +309,7 @@ int armv4_5_mmu_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, ch
 	}
 
 	free(buffer);
-	
+
 	return ERROR_OK;
 }
 
@@ -365,7 +365,7 @@ int armv4_5_mmu_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, ch
 			break;
 		default:
 			command_print(cmd_ctx, "error: unknown error");
-	}	
+	}
 
 	return ERROR_OK;
 }