- Fixes '<<' whitespace

- Replace ')\(<<\)\(\w\)' with ') \1 \2'.
- Replace '\(\w\)\(<<\)(' with '\1 \2 ('.
- Replace '\(\w\)\(<<\)\(\w\)' with '\1 \2 \3'.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2370 b42882b7-edfa-0310-969c-e2dbd0fdcd60

9 files changed, 79 insertions, 79 deletions

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 146f89f4..a58c0a7c 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -300,7 +300,7 @@ int dap_dp_read_reg(swjdp_common_t *swjdp, uint32_t *value, uint8_t reg_addr)
 int dap_ap_select(swjdp_common_t *swjdp,uint8_t apsel)
 {
 	uint32_t select;
-	select = (apsel<<24) & 0xFF000000;
+	select = (apsel << 24) & 0xFF000000;
 
 	if (select != swjdp->apsel)
 	{
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 2015c4d3..0466ff5b 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -37,15 +37,15 @@
 #define DP_SELECT		0x8
 #define DP_RDBUFF		0xC
 
-#define CORUNDETECT		(1<<0)
-#define SSTICKYORUN		(1<<1)
-#define SSTICKYERR		(1<<5)
-#define CDBGRSTREQ		(1<<26)
-#define CDBGRSTACK		(1<<27)
-#define CDBGPWRUPREQ	(1<<28)
-#define CDBGPWRUPACK	(1<<29)
-#define CSYSPWRUPREQ	(1<<30)
-#define CSYSPWRUPACK	(1<<31)
+#define CORUNDETECT		(1 << 0)
+#define SSTICKYORUN		(1 << 1)
+#define SSTICKYERR		(1 << 5)
+#define CDBGRSTREQ		(1 << 26)
+#define CDBGRSTACK		(1 << 27)
+#define CDBGPWRUPREQ	(1 << 28)
+#define CDBGPWRUPACK	(1 << 29)
+#define CSYSPWRUPREQ	(1 << 30)
+#define CSYSPWRUPACK	(1 << 31)
 
 #define	AP_REG_CSW		0x00
 #define AP_REG_TAR		0x04
@@ -61,13 +61,13 @@
 #define CSW_16BIT		1
 #define CSW_32BIT		2
 
-#define CSW_ADDRINC_MASK	(3<<4)
+#define CSW_ADDRINC_MASK	(3 << 4)
 #define CSW_ADDRINC_OFF		0
-#define CSW_ADDRINC_SINGLE	(1<<4)
-#define CSW_ADDRINC_PACKED	(2<<4)
-#define CSW_HPROT			(1<<25)
-#define CSW_MASTER_DEBUG	(1<<29)
-#define CSW_DBGSWENABLE		(1<<31)
+#define CSW_ADDRINC_SINGLE	(1 << 4)
+#define CSW_ADDRINC_PACKED	(2 << 4)
+#define CSW_HPROT			(1 << 25)
+#define CSW_MASTER_DEBUG	(1 << 29)
+#define CSW_DBGSWENABLE		(1 << 31)
 
 /* transaction mode */
 #define TRANS_MODE_NONE			0
diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 90442ea8..b314e02a 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -1330,7 +1330,7 @@ int evaluate_b_bl_blx_thumb(uint16_t opcode, uint32_t address, arm_instruction_t
 	if (((opc==0) || (opc==2)) && (offset & 0x00000400))
 		offset = 0xfffff800 | offset;
 	
-	target_address = address + 4 + (offset<<1);
+	target_address = address + 4 + (offset << 1);
 
 	switch (opc)
 	{
@@ -1348,7 +1348,7 @@ int evaluate_b_bl_blx_thumb(uint16_t opcode, uint32_t address, arm_instruction_t
 		case 2:
 			instruction->type = ARM_UNKNOWN_INSTUCTION;
 			mnemonic = "prefix";
-			target_address = offset<<12;
+			target_address = offset << 12;
 			break;
 		/* BL suffix */
 		case 3:
@@ -1371,8 +1371,8 @@ int evaluate_add_sub_thumb(uint16_t opcode, uint32_t address, arm_instruction_t
 	uint8_t Rd = (opcode >> 0) & 0x7;
 	uint8_t Rn = (opcode >> 3) & 0x7;
 	uint8_t Rm_imm = (opcode >> 6) & 0x7;
-	uint32_t opc = opcode & (1<<9);
-	uint32_t reg_imm  = opcode & (1<<10);
+	uint32_t opc = opcode & (1 << 9);
+	uint32_t reg_imm  = opcode & (1 << 10);
 	char *mnemonic;
 	
 	if (opc)
@@ -1731,8 +1731,8 @@ int evaluate_load_store_imm_thumb(uint16_t opcode, uint32_t address, arm_instruc
 	uint32_t offset = (opcode >> 6) & 0x1f;
 	uint8_t Rd = (opcode >> 0) & 0x7; 
 	uint8_t Rn = (opcode >> 3) & 0x7; 
-	uint32_t L = opcode & (1<<11);
-	uint32_t B = opcode & (1<<12);
+	uint32_t L = opcode & (1 << 11);
+	uint32_t B = opcode & (1 << 12);
 	char *mnemonic;
 	char suffix = ' ';
 	uint32_t shift = 2;
@@ -1759,13 +1759,13 @@ int evaluate_load_store_imm_thumb(uint16_t opcode, uint32_t address, arm_instruc
 		shift = 0;
 	}
 
-	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s%c r%i, [r%i, #0x%" PRIx32 "]", address, opcode, mnemonic, suffix, Rd, Rn, offset<<shift);
+	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s%c r%i, [r%i, #0x%" PRIx32 "]", address, opcode, mnemonic, suffix, Rd, Rn, offset << shift);
 	
 	instruction->info.load_store.Rd = Rd;
 	instruction->info.load_store.Rn = Rn;
 	instruction->info.load_store.index_mode = 0; /*offset*/
 	instruction->info.load_store.offset_mode = 0; /*immediate*/
-	instruction->info.load_store.offset.offset = offset<<shift;
+	instruction->info.load_store.offset.offset = offset << shift;
 
 	return ERROR_OK;
 }
@@ -1774,7 +1774,7 @@ int evaluate_load_store_stack_thumb(uint16_t opcode, uint32_t address, arm_instr
 {
 	uint32_t offset = opcode  & 0xff;
 	uint8_t Rd = (opcode >> 8) & 0x7; 
-	uint32_t L = opcode & (1<<11);
+	uint32_t L = opcode & (1 << 11);
 	char *mnemonic;
 
 	if (L)
@@ -1804,7 +1804,7 @@ int evaluate_add_sp_pc_thumb(uint16_t opcode, uint32_t address, arm_instruction_
 	uint32_t imm = opcode  & 0xff;
 	uint8_t Rd = (opcode >> 8) & 0x7; 
 	uint8_t Rn;
-	uint32_t SP = opcode & (1<<11);
+	uint32_t SP = opcode & (1 << 11);
 	char *reg_name;
 
 	instruction->type = ARM_ADD;
@@ -1833,7 +1833,7 @@ int evaluate_add_sp_pc_thumb(uint16_t opcode, uint32_t address, arm_instruction_
 int evaluate_adjust_stack_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
 	uint32_t imm = opcode  & 0x7f;
-	uint8_t opc = opcode & (1<<7);
+	uint8_t opc = opcode & (1 << 7);
 	char *mnemonic;
 
 	
@@ -1872,8 +1872,8 @@ int evaluate_breakpoint_thumb(uint16_t opcode, uint32_t address, arm_instruction
 int evaluate_load_store_multiple_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
 	uint32_t reg_list = opcode  & 0xff;
-	uint32_t L = opcode & (1<<11);
-	uint32_t R = opcode & (1<<8);
+	uint32_t L = opcode & (1 << 11);
+	uint32_t R = opcode & (1 << 8);
 	uint8_t Rn = (opcode >> 8) & 7;
 	uint8_t addr_mode = 0 /* IA */;
 	char reg_names[40];
@@ -1904,7 +1904,7 @@ int evaluate_load_store_multiple_thumb(uint16_t opcode, uint32_t address, arm_in
 			instruction->type = ARM_LDM;
 			mnemonic = "POP";
 			if (R)
-				reg_list |= (1<<15) /*PC*/;
+				reg_list |= (1 << 15) /*PC*/;
 		}
 		else
 		{
@@ -1912,14 +1912,14 @@ int evaluate_load_store_multiple_thumb(uint16_t opcode, uint32_t address, arm_in
 			mnemonic = "PUSH";
 			addr_mode = 3; /*DB*/
 			if (R)
-				reg_list |= (1<<14) /*LR*/;
+				reg_list |= (1 << 14) /*LR*/;
 		}
 	}
 
 	reg_names_p = reg_names;
 	for (i = 0; i <= 15; i++)
 	{
-		if (reg_list & (1<<i))
+		if (reg_list & (1 << i))
 			reg_names_p += snprintf(reg_names_p, (reg_names + 40 - reg_names_p), "r%i, ", i);
 	}
 	if (reg_names_p>reg_names)
@@ -1959,7 +1959,7 @@ int evaluate_cond_branch_thumb(uint16_t opcode, uint32_t address, arm_instructio
 	if (offset & 0x00000080)
 		offset = 0xffffff00 | offset;
 	
-	target_address = address + 4 + (offset<<1);
+	target_address = address + 4 + (offset << 1);
 
 	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tB%s 0x%8.8" PRIx32 , address, opcode,
 			 arm_condition_strings[cond], target_address);
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 3d75eed5..6c751332 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -138,13 +138,13 @@ extern int armv7m_blank_check_memory(struct target_s *target, uint32_t address,
  * Rd: destination register
  * SYSm: source special register
  */
-#define ARMV7M_T_MRS(Rd, SYSm)	((0xF3EF) | ((0x8000 | (Rd<<8) | SYSm) << 16)) 
+#define ARMV7M_T_MRS(Rd, SYSm)	((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16)) 
 
 /* Move from Register from Special Register  (Thumb mode) 32 bit Thumb2 instruction
  * Rd: source register
  * SYSm: destination special register
  */
-#define ARMV7M_T_MSR(SYSm, Rn)	((0xF380 | ( Rn<<8 )) | ((0x8800 | SYSm) << 16)) 
+#define ARMV7M_T_MSR(SYSm, Rn)	((0xF380 | ( Rn << 8 )) | ((0x8800 | SYSm) << 16)) 
 
 /* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK 
  * special-purpose register values  (Thumb mode) 16 bit Thumb2 instruction
@@ -153,8 +153,8 @@ extern int armv7m_blank_check_memory(struct target_s *target, uint32_t address,
  */
 #define I_FLAG 2
 #define F_FLAG 1  
-#define ARMV7M_T_CPSID(IF)	((0xB660 | (1<<8) | (IF&0x3)) | ((0xB660 | (1<<8) | (IF&0x3)) << 16)) 
-#define ARMV7M_T_CPSIE(IF)	((0xB660 | (0<<8) | (IF&0x3)) | ((0xB660 | (0<<8) | (IF&0x3)) << 16)) 
+#define ARMV7M_T_CPSID(IF)	((0xB660 | (1 << 8) | (IF&0x3)) | ((0xB660 | (1 << 8) | (IF&0x3)) << 16)) 
+#define ARMV7M_T_CPSIE(IF)	((0xB660 | (0 << 8) | (IF&0x3)) | ((0xB660 | (0 << 8) | (IF&0x3)) << 16)) 
 
 /* Breakpoint (Thumb mode) v5 onwards
  * Im: immediate value used by debugger
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 644f6816..6079b9eb 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -641,7 +641,7 @@ int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int
 
 		/* Make sure we are in Thumb mode */
 		buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
-			buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1<<24));
+			buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
 		armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
 		armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
 	}
@@ -1580,7 +1580,7 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jt
 	armv7m->swjdp_info.ap_tar_value = -1;
 	armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
 	armv7m->swjdp_info.memaccess_tck = 8;
-	armv7m->swjdp_info.tar_autoincr_block = (1<<12);	/* Cortex-M3 has 4096 bytes autoincrement range */
+	armv7m->swjdp_info.tar_autoincr_block = (1 << 12);	/* Cortex-M3 has 4096 bytes autoincrement range */
 
 	/* initialize arch-specific breakpoint handling */
 
diff --git a/src/target/cortex_m3.h b/src/target/cortex_m3.h
index ae772543..70605469 100644
--- a/src/target/cortex_m3.h
+++ b/src/target/cortex_m3.h
@@ -44,7 +44,7 @@ extern char* cortex_m3_state_strings[];
 #define DCB_DCRDR	0xE000EDF8
 #define DCB_DEMCR	0xE000EDFC
 
-#define DCRSR_WnR	(1<<16)	
+#define DCRSR_WnR	(1 << 16)	
 
 #define DWT_CTRL	0xE0001000
 #define DWT_COMP0	0xE0001020
@@ -65,23 +65,23 @@ extern char* cortex_m3_state_strings[];
 #define DWT_CTRL	0xE0001000
 
 /* DCB_DHCSR bit and field definitions */
-#define DBGKEY		(0xA05F<<16)
-#define C_DEBUGEN	(1<<0)
-#define C_HALT		(1<<1)
-#define C_STEP		(1<<2)
-#define C_MASKINTS	(1<<3)
-#define S_REGRDY	(1<<16)
-#define S_HALT		(1<<17)
-#define S_SLEEP		(1<<18)
-#define S_LOCKUP	(1<<19)
-#define S_RETIRE_ST	(1<<24)
-#define S_RESET_ST	(1<<25)
+#define DBGKEY		(0xA05F << 16)
+#define C_DEBUGEN	(1 << 0)
+#define C_HALT		(1 << 1)
+#define C_STEP		(1 << 2)
+#define C_MASKINTS	(1 << 3)
+#define S_REGRDY	(1 << 16)
+#define S_HALT		(1 << 17)
+#define S_SLEEP		(1 << 18)
+#define S_LOCKUP	(1 << 19)
+#define S_RETIRE_ST	(1 << 24)
+#define S_RESET_ST	(1 << 25)
 
 /* DCB_DEMCR bit and field definitions */
-#define	TRCENA			(1<<24)
-#define	VC_HARDERR		(1<<10)
-#define	VC_BUSERR		(1<<8)
-#define	VC_CORERESET	(1<<0)
+#define	TRCENA			(1 << 24)
+#define	VC_HARDERR		(1 << 10)
+#define	VC_BUSERR		(1 << 8)
+#define	VC_CORERESET	(1 << 0)
 
 #define NVIC_ICTR		0xE000E004
 #define NVIC_ISE0		0xE000E100
@@ -98,12 +98,12 @@ extern char* cortex_m3_state_strings[];
 #define NVIC_BFAR		0xE000ED38
 
 /* NVIC_AIRCR bits */
-#define AIRCR_VECTKEY		(0x5FA<<16)
-#define AIRCR_SYSRESETREQ	(1<<2)
-#define AIRCR_VECTCLRACTIVE	(1<<1)
-#define AIRCR_VECTRESET		(1<<0)
+#define AIRCR_VECTKEY		(0x5FA << 16)
+#define AIRCR_SYSRESETREQ	(1 << 2)
+#define AIRCR_VECTCLRACTIVE	(1 << 1)
+#define AIRCR_VECTRESET		(1 << 0)
 /* NVIC_SHCSR bits */
-#define SHCSR_BUSFAULTENA	(1<<17)
+#define SHCSR_BUSFAULTENA	(1 << 17)
 /* NVIC_DFSR bits */
 #define DFSR_HALTED			1
 #define DFSR_BKPT			2
@@ -112,10 +112,10 @@ extern char* cortex_m3_state_strings[];
 
 #define FPCR_CODE 0
 #define FPCR_LITERAL 1
-#define FPCR_REPLACE_REMAP  (0<<30)
-#define FPCR_REPLACE_BKPT_LOW  (1<<30)
-#define FPCR_REPLACE_BKPT_HIGH  (2<<30)
-#define FPCR_REPLACE_BKPT_BOTH  (3<<30)
+#define FPCR_REPLACE_REMAP  (0 << 30)
+#define FPCR_REPLACE_BKPT_LOW  (1 << 30)
+#define FPCR_REPLACE_BKPT_HIGH  (2 << 30)
+#define FPCR_REPLACE_BKPT_BOTH  (3 << 30)
 
 typedef struct  cortex_m3_fp_comparator_s
 {
diff --git a/src/target/mips32.c b/src/target/mips32.c
index 6c4bfb9a..aa6d921c 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -433,19 +433,19 @@ int mips32_enable_interrupts(struct target_s *target, int enable)
 	
 	if (enable)
 	{
-		if (!(dcr & (1<<4)))
+		if (!(dcr & (1 << 4)))
 		{
 			/* enable interrupts */
-			dcr |= (1<<4);
+			dcr |= (1 << 4);
 			update = 1;
 		}
 	}
 	else
 	{
-		if (dcr & (1<<4))
+		if (dcr & (1 << 4))
 		{
 			/* disable interrupts */
-			dcr &= ~(1<<4);
+			dcr &= ~(1 << 4);
 			update = 1;
 		}
 	}
diff --git a/src/target/mips32.h b/src/target/mips32.h
index 2d00aa81..ab47f731 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -94,9 +94,9 @@ typedef struct mips32_core_reg_s
 #define MIPS32_COP0_MF	0x00
 #define MIPS32_COP0_MT	0x04
 
-#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct)	(((opcode)<<26) |((rs)<<21)|((rt)<<16)|((rd)<<11)| ((shamt)<<6) | (funct))
-#define MIPS32_I_INST(opcode, rs, rt, immd)	(((opcode)<<26) |((rs)<<21)|((rt)<<16)|(immd))
-#define MIPS32_J_INST(opcode, addr)	(((opcode)<<26) |(addr))
+#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct)	(((opcode) << 26) |((rs) << 21)|((rt) << 16)|((rd) << 11)| ((shamt) << 6) | (funct))
+#define MIPS32_I_INST(opcode, rs, rt, immd)	(((opcode) << 26) |((rs) << 21)|((rt) << 16)|(immd))
+#define MIPS32_J_INST(opcode, addr)	(((opcode) << 26) |(addr))
 
 #define MIPS32_NOP					0
 #define MIPS32_ADDI(tar, src, val)	MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index 5985cfd3..7a64bd4d 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -285,16 +285,16 @@ int mips_ejtag_init(mips_ejtag_t *ejtag_info)
 			break;
 	}
 	LOG_DEBUG("EJTAG: features:%s%s%s%s%s%s%s",
-		ejtag_info->impcode & (1<<28) ? " R3k":    " R4k",
-		ejtag_info->impcode & (1<<24) ? " DINT":   "",
-		ejtag_info->impcode & (1<<22) ? " ASID_8": "",
-		ejtag_info->impcode & (1<<21) ? " ASID_6": "",
-		ejtag_info->impcode & (1<<16) ? " MIPS16": "",
-		ejtag_info->impcode & (1<<14) ? " noDMA":  " DMA",
-		ejtag_info->impcode & (1<<0)  ? " MIPS64": " MIPS32"
+		ejtag_info->impcode & (1 << 28) ? " R3k":    " R4k",
+		ejtag_info->impcode & (1 << 24) ? " DINT":   "",
+		ejtag_info->impcode & (1 << 22) ? " ASID_8": "",
+		ejtag_info->impcode & (1 << 21) ? " ASID_6": "",
+		ejtag_info->impcode & (1 << 16) ? " MIPS16": "",
+		ejtag_info->impcode & (1 << 14) ? " noDMA":  " DMA",
+		ejtag_info->impcode & (1 << 0)  ? " MIPS64": " MIPS32"
 	);
 
-	if ((ejtag_info->impcode & (1<<14)) == 0)
+	if ((ejtag_info->impcode & (1 << 14)) == 0)
 		LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
 
 	/* set initial state for ejtag control reg */