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authorDavid Brownell <dbrownell@users.sourceforge.net>2009-12-04 20:44:29 -0800
committerDavid Brownell <dbrownell@users.sourceforge.net>2009-12-04 20:44:29 -0800
commitaf1d7590edf04077aa8f22fba9097e0c68431f68 (patch)
tree6a7c76d69f8a176a5be8cdbf7ceebbe9871cc9d5 /src/target
parent3edcff8b8efff841dfe601e87f42de7fe7b4792b (diff)
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ARM: doc updates for main header
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target')
-rw-r--r--src/target/armv4_5.h14
1 files changed, 11 insertions, 3 deletions
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 56461e7e..a93087e8 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -30,7 +30,8 @@
#include <helper/command.h>
-/* These numbers match the five low bits of the *PSR registers on
+/**
+ * These numbers match the five low bits of the *PSR registers on
* "classic ARM" processors, which build on the ARMv4 processor
* modes and register set.
*/
@@ -49,7 +50,7 @@ enum arm_mode {
const char *arm_mode_name(unsigned psr_mode);
bool is_arm_mode(unsigned psr_mode);
-/* The PSR "T" and "J" bits define the mode of "classic ARM" cores */
+/** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
enum arm_state {
ARM_STATE_ARM,
ARM_STATE_THUMB,
@@ -95,6 +96,7 @@ struct arm
/** Handle to the SPSR; valid only in core modes with an SPSR. */
struct reg *spsr;
+ /** Support for arm_reg_current() */
const int *map;
/**
@@ -105,7 +107,10 @@ struct arm
*/
enum arm_mode core_type;
+ /** Record the current core mode: SVC, USR, or some other mode. */
enum arm_mode core_mode;
+
+ /** Record the current core state: ARM, Thumb, or otherwise. */
enum arm_state core_state;
/** Flag reporting unavailability of the BKPT instruction. */
@@ -128,7 +133,10 @@ struct arm
/* FIXME all these methods should take "struct arm *" not target */
+ /** Retrieve all core registers, for display. */
int (*full_context)(struct target *target);
+
+ /** Retrieve a single core register. */
int (*read_core_reg)(struct target *target, struct reg *reg,
int num, enum arm_mode mode);
int (*write_core_reg)(struct target *target, struct reg *reg,
@@ -140,7 +148,7 @@ struct arm
uint32_t CRn, uint32_t CRm,
uint32_t *value);
- /* Write coprocessor register. */
+ /** Write coprocessor register. */
int (*mcr)(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm,