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authormlu <mlu@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-04-02 12:16:19 +0000
committermlu <mlu@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-04-02 12:16:19 +0000
commitc008618be9f7588b7a0c72cd85adff317d2b4394 (patch)
tree3ce6c042fb76fe824184171abc271eef617a52c9 /src/target
parent923293928a518c695d9100279cdc05d0e1055414 (diff)
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Cortex-M3 cleanup and performance patch
git-svn-id: svn://svn.berlios.de/openocd/trunk@1438 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target')
-rw-r--r--src/target/cortex_swjdp.c11
1 files changed, 7 insertions, 4 deletions
diff --git a/src/target/cortex_swjdp.c b/src/target/cortex_swjdp.c
index 3e094d84..0f737ce0 100644
--- a/src/target/cortex_swjdp.c
+++ b/src/target/cortex_swjdp.c
@@ -183,6 +183,7 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
/* too expensive to call keep_alive() here */
+#if 0
/* Danger!!!! BROKEN!!!! */
scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
/* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
@@ -196,6 +197,8 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
LOG_ERROR("BUG: Why does this fail the first time????");
}
/* Why??? second time it works??? */
+#endif
+
scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
if ((retval=jtag_execute_queue())!=ERROR_OK)
return retval;
@@ -925,7 +928,7 @@ int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
/* because the DCB_DCRDR is used for the emulated dcc channel
* we gave to save/restore the DCB_DCRDR when used */
- ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr);
+ ahbap_read_system_u32(swjdp, DCB_DCRDR, &dcrdr);
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
@@ -937,8 +940,8 @@ int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
+ ahbap_write_system_u32(swjdp, DCB_DCRDR, dcrdr);
retval = swjdp_transaction_endcheck(swjdp);
- ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
return retval;
}
@@ -950,7 +953,7 @@ int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
/* because the DCB_DCRDR is used for the emulated dcc channel
* we gave to save/restore the DCB_DCRDR when used */
- ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr);
+ ahbap_read_system_u32(swjdp, DCB_DCRDR, &dcrdr);
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
@@ -962,8 +965,8 @@ int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR );
+ ahbap_write_system_u32(swjdp, DCB_DCRDR, dcrdr);
retval = swjdp_transaction_endcheck(swjdp);
- ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
return retval;
}