whitespace fixes

git-svn-id: svn://svn.berlios.de/openocd/trunk@1682 b42882b7-edfa-0310-969c-e2dbd0fdcd60

2 files changed, 13 insertions, 52 deletions

diff --git a/src/target/etb.c b/src/target/etb.c
index 8ccc5387..71514a5e 100644
--- a/src/target/etb.c
+++ b/src/target/etb.c
@@ -58,6 +58,7 @@ static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cm
 static int etb_set_instr(etb_t *etb, u32 new_instr)
 {
 	jtag_tap_t *tap;
+
 	tap = etb->tap;
 	if (tap==NULL)
 		return ERROR_FAIL;
@@ -73,10 +74,6 @@ static int etb_set_instr(etb_t *etb, u32 new_instr)
 
 		field.in_value = NULL;
 
-
-		
-
-
 		jtag_add_ir_scan(1, &field, TAP_INVALID);
 
 		free(field.out_value);
@@ -87,7 +84,7 @@ static int etb_set_instr(etb_t *etb, u32 new_instr)
 
 static int etb_scann(etb_t *etb, u32 new_scan_chain)
 {
-	if(etb->cur_scan_chain != new_scan_chain)
+	if (etb->cur_scan_chain != new_scan_chain)
 	{
 		scan_field_t field;
 
@@ -98,10 +95,6 @@ static int etb_scann(etb_t *etb, u32 new_scan_chain)
 
 		field.in_value = NULL;
 
-
-		
-
-
 		/* select INTEST instruction */
 		etb_set_instr(etb, 0x2);
 		jtag_add_dr_scan(1, &field, TAP_INVALID);
@@ -159,6 +152,7 @@ reg_cache_t* etb_build_reg_cache(etb_t *etb)
 static int etb_get_reg(reg_t *reg)
 {
 	int retval;
+
 	if ((retval = etb_read_reg(reg)) != ERROR_OK)
 	{
 		LOG_ERROR("BUG: error scheduling etm register read");
@@ -188,25 +182,21 @@ static int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
 	fields[0].out_value = NULL;
 	u8 tmp[4];
 	fields[0].in_value = tmp;
-	
 
 	fields[1].tap = etb->tap;
 	fields[1].num_bits = 7;
 	fields[1].out_value = malloc(1);
 	buf_set_u32(fields[1].out_value, 0, 7, 4);
 	fields[1].in_value = NULL;
-	
 
 	fields[2].tap = etb->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = malloc(1);
 	buf_set_u32(fields[2].out_value, 0, 1, 0);
 	fields[2].in_value = NULL;
-	
 
 	jtag_add_dr_scan(3, fields, TAP_INVALID);
 
-
 	for (i = 0; i < num_frames; i++)
 	{
 		/* ensure nR/W reamins set to read */
@@ -246,35 +236,20 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 	fields[0].tap = etb_reg->etb->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = reg->value;
-
 	fields[0].in_value = NULL;
 
-
-	
-
-
 	fields[1].tap = etb_reg->etb->tap;
 	fields[1].num_bits = 7;
 	fields[1].out_value = malloc(1);
 	buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
-
 	fields[1].in_value = NULL;
 
-
-	
-
-
 	fields[2].tap = etb_reg->etb->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = malloc(1);
 	buf_set_u32(fields[2].out_value, 0, 1, 0);
-
 	fields[2].in_value = NULL;
 
-
-	
-
-
 	jtag_add_dr_scan(3, fields, TAP_INVALID);
 
 	/* read the identification register in the second run, to make sure we
@@ -301,6 +276,7 @@ int etb_read_reg(reg_t *reg)
 int etb_set_reg(reg_t *reg, u32 value)
 {
 	int retval;
+
 	if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
 	{
 		LOG_ERROR("BUG: error scheduling etm register write");
@@ -317,6 +293,7 @@ int etb_set_reg(reg_t *reg, u32 value)
 int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
 {
 	int retval;
+
 	etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -343,24 +320,14 @@ int etb_write_reg(reg_t *reg, u32 value)
 	fields[0].num_bits = 32;
 	fields[0].out_value = malloc(4);
 	buf_set_u32(fields[0].out_value, 0, 32, value);
-
 	fields[0].in_value = NULL;
 
-
-	
-
-
 	fields[1].tap = etb_reg->etb->tap;
 	fields[1].num_bits = 7;
 	fields[1].out_value = malloc(1);
 	buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
-
 	fields[1].in_value = NULL;
 
-
-	
-
-
 	fields[2].tap = etb_reg->etb->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = malloc(1);
@@ -368,12 +335,6 @@ int etb_write_reg(reg_t *reg, u32 value)
 
 	fields[2].in_value = NULL;
 
-
-	
-
-
-	jtag_add_dr_scan(3, fields, TAP_INVALID);
-
 	free(fields[0].out_value);
 	free(fields[1].out_value);
 	free(fields[2].out_value);
@@ -424,12 +385,12 @@ static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cm
 	}
 
 	tap = jtag_TapByString( args[1] );
-	if( tap == NULL ){
+	if (tap == NULL)
+	{
 		command_print(cmd_ctx, "Tap: %s does not exist", args[1] );
 		return ERROR_FAIL;
 	}
 
-
 	if (arm7_9->etm_ctx)
 	{
 		etb_t *etb = malloc(sizeof(etb_t));
diff --git a/src/target/etm.h b/src/target/etm.h
index 8e5812b8..26e0d764 100644
--- a/src/target/etm.h
+++ b/src/target/etm.h
@@ -62,7 +62,7 @@ enum
 	ETM_SEQUENCER_STATE = 0x67,
 	ETM_EXTERNAL_OUTPUT = 0x68,
 	ETM_CONTEXTID_COMPARATOR_VALUE = 0x6c,
-	ETM_CONTEXTID_COMPARATOR_MASK = 0x6f,	
+	ETM_CONTEXTID_COMPARATOR_MASK = 0x6f,
 };
 
 typedef struct etm_reg_s
@@ -77,7 +77,7 @@ typedef enum
 	ETM_PORT_4BIT		= 0x00,
 	ETM_PORT_8BIT		= 0x10,
 	ETM_PORT_16BIT		= 0x20,
-	ETM_PORT_WIDTH_MASK	= 0x70, 
+	ETM_PORT_WIDTH_MASK	= 0x70,
 	/* Port modes */
 	ETM_PORT_NORMAL    = 0x00000,
 	ETM_PORT_MUXED     = 0x10000,
@@ -146,11 +146,11 @@ typedef struct etm_context_s
 	etm_capture_driver_t *capture_driver;	/* driver used to access ETM data */
 	void *capture_driver_priv;		/* capture driver private data */
 	u32 trigger_percent;			/* percent of trace buffer to be filled after the trigger */
-	trace_status_t capture_status;	/* current state of capture run */ 
+	trace_status_t capture_status;	/* current state of capture run */
 	etmv1_trace_data_t *trace_data;	/* trace data */
 	u32 trace_depth;				/* number of trace cycles to be analyzed, 0 if no trace data available */
 	etm_portmode_t portmode;		/* normal, multiplexed or demultiplexed */
-	etmv1_tracemode_t tracemode;	/* type of information the trace contains (data, addres, contextID, ...) */ 
+	etmv1_tracemode_t tracemode;	/* type of information the trace contains (data, addres, contextID, ...) */
 	armv4_5_state_t core_state;		/* current core state (ARM, Thumb, Jazelle) */
 	image_t *image;					/* source for target opcodes */
 	u32 pipe_index;					/* current trace cycle */
@@ -158,10 +158,10 @@ typedef struct etm_context_s
 	int data_half;					/* port half on a 16 bit port */
 	u32 current_pc;					/* current program counter */
 	u32 pc_ok;						/* full PC has been acquired */
-	u32 last_branch;				/* last branch address output */ 
+	u32 last_branch;				/* last branch address output */
 	u32 last_branch_reason;			/* branch reason code for the last branch encountered */
 	u32 last_ptr;					/* address of the last data access */
-	u32 ptr_ok;						/* whether last_ptr is valid */ 
+	u32 ptr_ok;						/* whether last_ptr is valid */
 	u32 context_id;					/* context ID of the code being traced */
 	u32 last_instruction;			/* index of last instruction executed (to calculate cycle timings) */
 } etm_context_t;