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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-29 12:58:30 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-29 12:58:30 -0800 |
| commit | e456da073abeb2b45fdeb7ef48bf5f905221524a (patch) | |
| tree | a13dd29b1e5fa8f3847fb689bf7f769485f604a8 /src/target | |
| parent | 8c2846ed450a6280aa3fa8b58e796f20405c842d (diff) | |
| download | openocd_libswd-e456da073abeb2b45fdeb7ef48bf5f905221524a.tar.gz openocd_libswd-e456da073abeb2b45fdeb7ef48bf5f905221524a.tar.bz2 openocd_libswd-e456da073abeb2b45fdeb7ef48bf5f905221524a.tar.xz openocd_libswd-e456da073abeb2b45fdeb7ef48bf5f905221524a.zip | |
XScale: debug entry uses new register mapping
Use the new mapping interfaces in the debug entry path.
SPSR and the banked registers now have smaller and faster
accessors ... use them.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target')
| -rw-r--r-- | src/target/xscale.c | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/src/target/xscale.c b/src/target/xscale.c index b4cb4ffb..0e58f575 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -973,12 +973,11 @@ static int xscale_debug_entry(struct target *target) arm_mode_name(armv4_5->core_mode)); /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */ - if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS)) - { + if (armv4_5->spsr) { xscale_receive(target, buffer, 8); - buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]); - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1; + buf_set_u32(armv4_5->spsr->value, 0, 32, buffer[7]); + armv4_5->spsr->dirty = false; + armv4_5->spsr->valid = true; } else { @@ -986,12 +985,14 @@ static int xscale_debug_entry(struct target *target) xscale_receive(target, buffer, 7); } - /* move data from buffer to register cache */ + /* move data from buffer to right banked register in cache */ for (i = 8; i <= 14; i++) { - buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, buffer[i - 8]); - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1; + struct reg *r = arm_reg_current(armv4_5, i); + + buf_set_u32(r->value, 0, 32, buffer[i - 8]); + r->dirty = false; + r->valid = true; } /* examine debug reason */ |