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author | Øyvind Harboe <oyvind.harboe@zylin.com> | 2009-10-14 11:14:04 +0200 |
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committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2009-10-14 11:14:04 +0200 |
commit | 4490a42a09c16673769cada0db2d654fcb93edad (patch) | |
tree | c7bde20036f42f501ec0ceea542623fc2b57a8bb /src | |
parent | 44e9200d0a51b432aa8f1449046780fa8c7a6069 (diff) | |
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Work in progress on arm11 reset. Assert srst.
Diffstat (limited to 'src')
-rw-r--r-- | src/target/arm11.c | 56 |
1 files changed, 50 insertions, 6 deletions
diff --git a/src/target/arm11.c b/src/target/arm11.c index f46e424b..94d5fb1b 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -1200,18 +1200,62 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl int arm11_assert_reset(target_t *target) { FNC_INFO; + int retval; - /* FIX! we really should assert srst here, but - * how do we reset the target into the halted state? - * - * Also arm11 behaves "funny" when srst is asserted - * (as of writing the rules are not understood). - */ + arm11_common_t * arm11 = target->arch_info; + retval = arm11_check_init(arm11, NULL); + if (retval != ERROR_OK) + return retval; + + target->state = TARGET_UNKNOWN; + + /* we would very much like to reset into the halted, state, + * but resetting and halting is second best... */ if (target->reset_halt) { CHECK_RETVAL(target_halt(target)); } + + /* srst is funny. We can not do *anything* else while it's asserted + * and it has unkonwn side effects. Make sure no other code runs + * meanwhile. + * + * Code below assumes srst: + * + * - Causes power-on-reset (but of what parts of the system?). Bug + * in arm11? + * + * - Messes us TAP state without asserting trst. + * + * - There is another bug in the arm11 core. When you generate an access to + * external logic (for example ddr controller via AHB bus) and that block + * is not configured (perhaps it is still held in reset), that transaction + * will never complete. This will hang arm11 core but it will also hang + * JTAG controller. Nothing, short of srst assertion will bring it out of + * this. + * + * Mysteries: + * + * - What should the PC be after an srst reset when starting in the halted + * state? + */ + + jtag_add_reset(0, 1); + jtag_add_reset(0, 0); + + /* How long do we have to wait? */ + jtag_add_sleep(5000); + + /* un-mess up TAP state */ + jtag_add_tlr(); + + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + { + return retval; + } + return ERROR_OK; } |