LPC1768 updates, IAR board support

Fix some issues with the generic LPC1768 config file:

 - Handle the post-reset clock config:  4 MHz internal RC, no PLL.
   This affects flash and JTAG clocking.

 - Remove JTAG adapter config; they don't all support trst_and_srst

 - Remove the rest of the bogus "reset-init" event handler.

 - Allow explicit CCLK configuration, instead of assuming 12 MHz;
   some boards will use 100 Mhz (or the post-reset 4 MHz).

 - Simplify: rely on defaults for endianness and IR-Capture value

 - Update some comments too

Build on those fixes to make a trivial config for the IAR LPC1768
kickstart board (by Olimex) start working.

Also, add doxygen to the lpc2000 flash driver, primarily to note a
configuration problem with driver: it wrongly assumes the core clock
rate never changes.  Configs that are safe for updating flash after
"reset halt" will thus often be unsafe later ... e.g. for LPC1768,
after switching to use PLL0 at 100 MHz.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>

1 files changed, 9 insertions, 1 deletions

diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c
index 6674f171..438ab544 100644
--- a/src/flash/nor/lpc2000.c
+++ b/src/flash/nor/lpc2000.c
@@ -33,7 +33,15 @@
 #include <target/armv7m.h>
 
 
-/* flash programming support for NXP LPC17xx and LPC2xxx devices
+/**
+ * @file
+ * flash programming support for NXP LPC17xx and LPC2xxx devices.
+ *
+ * @todo Provide a way to update CCLK after declaring the flash bank.
+ * The value which is correct after chip reset will rarely still work
+ * right after the clocks switch to use the PLL (e.g. 4MHz --> 100 MHz).
+ */
+/*
  * currently supported devices:
  * variant 1 (lpc2000_v1):
  * - 2104 | 5 | 6