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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-02 22:57:07 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-02 23:08:42 -0800 |
| commit | 7e18d96d03e39ef55c0b1d420b53247a29fef24b (patch) | |
| tree | 95a502ecf96d3ea9045184a6f001298aaffb0702 /src | |
| parent | 6ec5b9c674489b4bd257c41142f100401c8d2025 (diff) | |
| download | openocd_libswd-7e18d96d03e39ef55c0b1d420b53247a29fef24b.tar.gz openocd_libswd-7e18d96d03e39ef55c0b1d420b53247a29fef24b.tar.bz2 openocd_libswd-7e18d96d03e39ef55c0b1d420b53247a29fef24b.tar.xz openocd_libswd-7e18d96d03e39ef55c0b1d420b53247a29fef24b.zip | |
ARM11: don't expose RDTR
Don't expose the RDTR register through the register cache any
more. If anyone wants Tcl scripts to be able to use DCC based
communication with app code in the target, this wouldn't do it.
Bugfix: don't trust the Tcl-accessible version of DSCR to
flag whether RDTR needs to be restored when resuming.
Diffstat (limited to 'src')
| -rw-r--r-- | src/target/arm11.c | 21 | ||||
| -rw-r--r-- | src/target/arm11.h | 5 |
2 files changed, 11 insertions, 15 deletions
diff --git a/src/target/arm11.c b/src/target/arm11.c index 65ec47f1..d08911e8 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -51,7 +51,6 @@ enum arm11_regtype /* debug regs */ ARM11_REGISTER_DSCR, ARM11_REGISTER_WDTR, - ARM11_REGISTER_RDTR, }; @@ -69,14 +68,12 @@ static const struct arm11_reg_defs arm11_reg_defs[] = /* Debug Registers */ {"dscr", 0, -1, ARM11_REGISTER_DSCR}, {"wdtr", 0, -1, ARM11_REGISTER_WDTR}, - {"rdtr", 0, -1, ARM11_REGISTER_RDTR}, }; enum arm11_regcache_ids { ARM11_RC_DSCR, ARM11_RC_WDTR, - ARM11_RC_RDTR, ARM11_RC_MAX, }; @@ -254,20 +251,15 @@ static int arm11_debug_entry(struct arm11_common *arm11, uint32_t dscr) return retval; /* maybe save rDTR */ - - /* check rDTRfull in DSCR */ - - if (dscr & ARM11_DSCR_RDTR_FULL) + arm11->is_rdtr_saved = !!(dscr & ARM11_DSCR_RDTR_FULL); + if (arm11->is_rdtr_saved) { /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */ - retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR)); + retval = arm11_run_instr_data_from_core_via_r0(arm11, + 0xEE100E15, &arm11->saved_rdtr); if (retval != ERROR_OK) return retval; } - else - { - arm11->reg_list[ARM11_RC_RDTR].valid = 0; - } /* REVISIT Now that we've saved core state, there's may also * be MMU and cache state to care about ... @@ -365,7 +357,7 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp) /* maybe restore rDTR */ - if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty) + if (arm11->is_rdtr_saved) { arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); @@ -376,7 +368,8 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp) uint8_t Ready = 0; /* ignored */ uint8_t Valid = 0; /* ignored */ - arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0); + arm11_setup_field(arm11, 32, &arm11->saved_rdtr, + NULL, chain5_fields + 0); arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1); arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2); diff --git a/src/target/arm11.h b/src/target/arm11.h index e5c92def..cde6c787 100644 --- a/src/target/arm11.h +++ b/src/target/arm11.h @@ -26,7 +26,7 @@ #include "armv4_5.h" #include "arm_dpm.h" -#define ARM11_REGCACHE_COUNT 3 +#define ARM11_REGCACHE_COUNT 2 #define ARM11_TAP_DEFAULT TAP_INVALID @@ -62,6 +62,9 @@ struct arm11_common uint32_t last_dscr; /**< Last retrieved DSCR value; Use only for debug message generation */ + uint32_t saved_rdtr; + + bool is_rdtr_saved; bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */ /** \name Shadow registers to save debug state */ |